Physical Design Engineer Intern

Ambarella • Headquarters, KY

6d

About The Position

The Physical Design Engineer Intern will be an integral part of the physical design team, contributing to physical design implementation and verification for Ambarella’s low-power AI SoC, from netlist to GDSII. Work covers the SoC implementation process at the block and/or full-chip level.

Responsibilities

• Contribute to floor-planning, automated place and route, and static timing analysis.
• Implement engineering change orders (ECOs) and perform signal-integrity and EM/IR analyses.
• Perform formal verification and physical layout verification, including LVS, DRC, and DFM, at the block and/or full-chip level.

What This Job Offers

• Career Level: Intern
• Education Level: No Education Listed