Physical Design Engineer II (eInfochips Inc)

Arrow Electronics•San Jose, CA

34d•Onsite

About The Position

This role involves executing synthesis, place and route (PNR), and static timing analysis (STA) for assigned partitions of an ASIC chip, adhering to strict schedules and design goals. The engineer will collaborate closely with architects, RTL designers, and DFT engineers to resolve implementation and signoff issues. Responsibilities include closing EM/IR, driving LEC, and physical verification signoff for partitions, in coordination with methodology owners. The position also requires partnering with the design team to identify and address potential physical design challenges, contributing to the refinement of implementation and physical design methodologies, and troubleshooting flow issues with EDA vendors.

Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field, or equivalent practical experience.
7+ years of hands-on experience in physical design and implementation, encompassing synthesis, PnR, timing convergence and physical verification.
Proficiency in utilizing Electronic Design Automation (EDA) tools such as Innovus, Tempus, and Quantus, as well as a deep understanding of physical design flows and methodologies.

Nice To Haves

7+ years of experience in physical design roles and related activities.
Proven ability to adhere to tight schedules and implement low-power design techniques.
Experience in System-on-Chip (SoC) design and implementation.
Expertise in sub-7nm node technologies.
Familiarity with industry-standard EDA tools and their capabilities.
Strong scripting skills in TCL to develop custom flows and methodologies on standard EDA tools from Cadence/Synopsys.

Responsibilities

Execute synthesis, PNR, and STA for assigned partitions of ASIC chip adhering to strict schedules and design goals.
Work closely with architects, RTL designers, and DFT engineers to resolve implementation and signoff issues across your blocks.
Help close EM/IR, drive LEC and physical verification signoff for your partitions in coordination with methodology owners.
Partner with the design team to proactively identify and address potential physical design challenges, enabling efficient iteration and convergence.
Contribute to the refinement of other implementation and physical design methodologies, encompassing synthesis, place and route (PnR), electromigration and IR (EMIR), power delivery network (PDN), and logical equivalence checking (LEC).
Troubleshoot flow issues and collaborate with EDA vendors to resolve them as needed.