New Graduate Engineer, ASIC Design (Starshield)

SpaceX•Hawthorne, CA

15h•$125,000 - $150,000

About The Position

As an ASIC Design Engineer on the Starshield team, you will be working on advanced development programs in support of U.S. National Security. In this role, you will be developing cutting-edge next-generation FPGAs and ASICs for deployment in space and ground infrastructures around the globe. You will work in a highly collaborative and fast-paced environment, where we are exploring unsolved problems and applying the SpaceX mindset of iterating rapidly to go from design and demo to operational capability at lightning pace.

Requirements

Bachelor’s degree in electrical engineering, computer engineering, or computer science.
Graduating with a bachelor’s degree, master’s degree, or PhD in 2026 or 2027.
1+ years of experience in RTL implementation and/or FPGA/ASIC development.

Nice To Haves

Experience solving problems including clock domain crossings and power optimization.
Experience developing complex ASICs.
Experience with multicore CPU subsystem design.
Experience with standard bus protocols (e.g. AXI, AHB, etc.).
Experience with embedded processors.
Experience with high speed and low power design techniques.
Scripting skills (Python, TCL etc.).
Experience with EDA tools such as HDL simulators (e.g. VCS, Questa, IES), HDL Lint tools (e.g. Spyglass) and FPGA tools (e.g. Xilinx Vivado, Altera Quartus II).
Ability to work in a dynamic environment with changing needs and requirements.
Team-player, can-do attitude and ability to work well in a group environment while still contributing on an individual basis.
Enjoy being challenged and learning new skills.

Responsibilities

Design digital ASICs and/or FPGAs for Starshield projects.
Evaluate architectural trade-offs based on features, performance requirements and system limitations. Derive specifications for the subsystems and circuits, and work with modem/DSP and RFIC engineers to partition functions between hardware and software domains.
Define micro-architecture, implement the RTL in Verilog/System Verilog, integrate that in top level and deliver the fully verified, synthesis/timing clean design.
Work closely with verification team to ensure all aspects of the design are covered and verified.
Provide timing constraints for those IPs and support the physical implementation team (synthesis, timing closure, formality check).
Participate in silicon bring-up and validation. Assist in the development of automated test lab equipment for lab measurements.