Engineer, ASIC Physical Design

Micron Technology • Minneapolis, MN

1d • $142,506 - $176,000 • Hybrid

About The Position

Design, analyze, and implement digital circuits used in the development of memory products. Develop groundbreaking silicon-to-systems solutions – right from technology development and advanced memory designs to product development, systems design and validation resulting in world class memory solutions. Collaborate with Micron’s various design and verification teams globally to proactively design products that optimize all manufacturing functions and assure the best cost, quality, reliability, time-to-market, and customer satisfaction. Contribute to the development of new product opportunities by assisting with the overall design, layout, and optimization of Memory/Logic/Analog circuits. Chip floor-planning, physical design, IP integration, static timing analysis, design validation, and required tape-out revisions. Implement and manage the layout process including floor-planning, placement, and routing, physical verification, and final signoff for tape out.

Requirements

• Master’s degree in Electrical Engineering, Computer Engineering or related field.
• Chip floor planning, placement and routing including power and clock routing or knowledge of how to modify existing scripts to manipulate the existing flow scripts.
• Placement of macros, pins, blockage layers.
• Static timing analysis including using Tempus (cadence) or Primetime (synopsys).
• Place and Route: Cadence tools (Innovus/Tempus) or Synopsys tools (ICC2 or Fusion Compiler/Primetime).
• Physical verification: Mentor tools (Calibre) or Synopsys tools (IC Validator or Hercules).
• Customized flow development, including the use of Tcl and Cshell commands

Responsibilities

• Chip floor planning, placement and routing including power and clock routing or knowledge of how to modify existing scripts to manipulate the existing flow scripts.
• Placement of macros, pins, blockage layers.
• Static timing analysis including using Tempus (cadence) or Primetime (synopsys).
• Place and Route: Cadence tools (Innovus/Tempus) or Synopsys tools (ICC2 or Fusion Compiler/Primetime).
• Physical verification: Mentor tools (Calibre) or Synopsys tools (IC Validator or Hercules).
• Customized flow development, including the use of Tcl and Cshell commands

Benefits

• Choice of medical, dental and vision plans
• Benefit programs that help protect your income if you are unable to work due to illness or injury
• Paid family leave
• Robust paid time-off program
• Paid holidays

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level