ASIC Physical Design Engineer

CiscoMaynard, MA
$135,800 - $252,000

About The Position

The application window is expected to close on: 06/26/2026. Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received. Meet the Team Acacia, part of Cisco, provides innovative silicon-based high-speed optical interconnect products to accelerate network scalability through advancements in performance, capacity, and cost. Our DSP ASICs, silicon photonic PICs, and coherent modules empower cloud and service providers to meet the fast-growing demand for data. We have assembled a team of cross-functional experts capable of solving the challenges of next-generation optical interconnects, resulting in industry-leading, award-winning products. Come join us at Cisco, named the #1 world’s best workplaces, and do purposeful work that makes a global impact and gives back to a company culture that empowers an inclusive future for all. Your Impact As a Physical Design Engineer with Acacia, you will focus on the technical execution of high-performance ASIC designs. Working as an individual contributor, you will lead the RTL-to-GDSII implementation flow for advanced semiconductor nodes, ensuring that Acacia’s networking platforms meet rigorous power, performance, and area (PPA) targets. You will be responsible for the successful delivery of assigned blocks from specification through to tapeout.

Requirements

  • Bachelors degree in Engineering + 5 years of related experience, or Masters degree in Engineering+ 3 years of related experience.
  • Demonstrated experience in ASIC physical design and implementation.
  • Experience working with hierarchical floor planning, clock and power distribution, global signal and I/O planning along with physical convergence, timing closure, and hierarchical design methodology.
  • Prior experience with power integrity analysis and working on designs >100M gates in advanced nodes.

Nice To Haves

  • Experience with Scripting using languages such as TCL, Perl, Python, etc.
  • Place & Route experience using tools such as Cadence Innovus or Synopsys ICC2.
  • Experience with formal equivalence check, timing closure, signal integrity, EMIR, physical verification DRC/LVS
  • Synthesis experience including Synopsys DC/FC.
  • Formal Verification experience using tools such Synopsys Formality or Cadence LEC
  • Experience with Static Timing Analysis including tools such as Tempus.
  • Experience with block level EMIR closure.
  • Physical Verification experience including tools such as Synopsys ICV or Mentor Calibre.

Responsibilities

  • Implement end-to-end RTL-to-GDSII implementation for advanced nodes (sub-7nm to 2nm)
  • Perform hierarchical floor planning, place and route, and clock/power distribution
  • Conduct static timing analysis (STA) and drive timing closure for multi-mode/multi-corner designs
  • Lead the physical design of assigned blocks, ensuring quality and alignment to project timelines
  • Develop and maintain automated scripts to improve design flow efficiency and methodology
  • Collaborate with RTL and DFT teams to debug and resolve complex physical implementation issues
  • Implement test plans and participate in design reviews to ensure robust, high-quality work
  • Implement ECO strategies and support sign-off processes
  • Contribute to the refinement of design methodologies and best practices within the engineering team
  • Document functional specifications and track progress for assigned project landmarks

Benefits

  • medical, dental and vision insurance
  • a 401(k) plan with a Cisco matching contribution
  • paid parental leave
  • short and long-term disability coverage
  • basic life insurance
  • 10 paid holidays per full calendar year, plus 1 floating holiday for non-exempt employees
  • 1 paid day off for employee’s birthday, paid year-end holiday shutdown, and 4 paid days off for personal wellness determined by Cisco
  • 16 days of paid vacation time per full calendar year, accrued at rate of 4.92 hours per pay period for full-time employees (non-exempt)
  • flexible vacation time off program (exempt)
  • 80 hours of sick time off provided on hire date and each January 1st thereafter, and up to 80 hours of unused sick time carried forward from one calendar year to the next
  • Optional 10 paid days per full calendar year to volunteer
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