ASIC Design Engineer (eInfochips)

Arrow Electronics•Austin, TX

22h•Remote

About The Position

eInfochips, an Arrow company (Fortune #154), is a leading global provider of product engineering and semiconductor design services. With a rich history of over two decades, eInfochips has developed over 500+ products and achieved 40 million deployments in 140 countries, consistently driving technological innovation across multiple verticals. The company holds strategic technology partnerships with industry leaders such as Qualcomm, NVIDIA, NXP, Analog Devices, Texas Instruments, Amazon, Microsoft, and Google. Supported by Arrow's $38 billion in revenues, 22,000 employees, and 345 locations serving over 80 countries, eInfochips is well-positioned to accelerate connected product innovation for its more than 150,000 global clients. eInfochips serves as a catalyst for Arrow's Sensor-to-Sunset initiative, providing comprehensive edge-to-cloud capabilities to its clients. Visit www.einfochips.com to explore their portfolio of product engineering services across various industries and verticals.

Requirements

Proficient in Verilog/System Verilog coding constructs.
Knowledge of front-end tools (Verilog simulators, Connectivity tools, CDC checkers, low power static checkers, linting)
Experience with high speed PCIe designs and protocols.
Experience with Industry standard interface protocols such as AXI, APB, etc.
Experience with ARM Fabric IPs.
Experience with IPXACT.
Understanding of Computer Architecture fundamentals.
Ability to write scripts using Python, Tcl, Perl etc.
Experience in EDA tools such as VCS, VCLP, Spyglass Lint, Questa CDC, Fusion Compiler, Design Compiler, Genus.
Proficiency with UPF (Low power intent).
Proficiency in clock crossing techniques.
Knowledge of Static Timing Analysis and understanding of timing signoff fundamentals.
Good in understanding RTL Design and Digital concepts
Strong experience with EDA tools: Fusion Compiler, CDC
Scripting: Pearl, Python, TCL
At least 5+ years of experience in Verilog Design
AMBA AXI bus along-with ARM or C based processor

Nice To Haves

Seeking candidate with Fusion Compiler and Scripting experience.

Responsibilities

Proficient in Verilog/System Verilog coding constructs.
Experience with high speed PCIe designs and protocols.
Experience with Industry standard interface protocols such as AXI, APB, etc.
Experience with ARM Fabric IPs.
Experience with IPXACT.
Understanding of Computer Architecture fundamentals.
Ability to write scripts using Python, Tcl, Perl etc.
Proficiency with UPF (Low power intent).
Proficiency in clock crossing techniques.
Knowledge of Static Timing Analysis and understanding of timing signoff fundamentals.
Ensure customer satisfaction.
Reporting to customers on daily or weekly progress effectively.