Microarchitecture and Design Engineer - AI SoC

Intel•Folsom, CA

1d•Hybrid

About The Position

Intel’s AI SoC organization develops products for AI applications ranging from edge devices to data center accelerators. This engineer contributes to the design and development of next-generation AI hardware, defining and implementing logic-block architecture and microarchitecture features and supporting SoC product development. The role involves RTL design, simulation, design quality checks, optimization, IP integration, verification support, and secure development practices. The position is eligible for Intel’s hybrid work model, splitting time between the assigned Intel site and off-site work.

Requirements

Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related field, plus at least 1 year of hands-on experience in logic design, RTL coding, and simulation; experience may be gained through internships, academic projects, coursework, or hands-on training; OR a master’s degree in Electrical Engineering, Computer Engineering, or a related field with no prior professional experience.
Proficiency in RTL coding languages such as Verilog or VHDL.
Familiarity with logic design tools and methodologies for synthesis, timing analysis, and power optimization.
Knowledge of SoC design principles and IP integration.

Nice To Haves

Strong analytical and problem-solving skills, with attention to detail.
Effective communication and collaboration skills for cross-functional teamwork.
Interest in contributing to secure design practices and quality assurance processes.

Responsibilities

Develop logic design, RTL coding, and simulation for SoC designs.
Define and implement architecture and microarchitecture features for logic blocks.
Perform quality checks across RTL, timing, power, and design integrity to meet performance goals.
Optimize RTL logic to meet power, performance, area, and timing targets.
Collaborate with IP providers to integrate and validate IPs at the SoC level.
Review and contribute to verification plans and ensure design features are comprehensively tested.
Identify and resolve RTL test failures to ensure feature correctness.
Employ secure development practices to address design security objectives and threats.
Drive quality assurance compliance for seamless IP and SoC handoff throughout the design flow.