Memory PHY RTL Design Engineer

Advanced Micro Devices, Inc•Markham, ON

21d•Hybrid

About The Position

The Memory PHY team is looking for a passionate and experienced Design Engineer for RTL and Firmware development of high-speed LPDDR, DDR IPs. Be a part of the definition, design and development phase of industry-leading Memory PHYs and interface IP. This opportunity includes creation of new IO designs as well as working on multiple designs and enhancing methodologies in parallel. Be a part of a team that delivers Industry leading IP and help our experts in RTL, FW, circuit, and architecture teams develop leading edge and differentiating IPs.

Requirements

Digital design engineering experience
Excellent knowledge of Verilog, System Verilog, C and a scripting language; experience with Python, Perl and TCL is a plus
Proficient in debugging firmware and RTL code using simulation tools
Proficient in using UVM testbenches and working in Linux and Windows environments
Knowledge of clocking architectures, synchronization, and CDC methodology
Strong understanding of computer organization/architecture.
Bachelors or Masters degree in Computer Engineering/Electrical Engineering

Nice To Haves

SERDES, DDR, Memory Controller, or MAC Design experience is preferred
Mixed signal RTL experience is a plus
Exposure to leadership or mentorship is an asset

Responsibilities

Microarchitectural design and RTL implementation of IP features.
Synthesis, STA, CDC/RDC, UPF Design/Simulation, Power optimization, Gate sim.
PHY Digital Architecture development from pathfinding, coding, verification to physical implementation
Collaborate with Firmware team to develop firmware sequences and algorithms
Analyze RTL design for power optimization and timing optimization
Collaborate with Design Verification team to execute on design features Timing Synthesis & Drive Physical implementation
Participate in design specification and RTL code reviews.