Silicon Design Engineer - Memory/PHY (DDR/PHY)

Advanced Micro Devices, IncAustin, TX
Onsite

About The Position

At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.

Requirements

  • Highly experienced RTL design engineer with strong technical judgment and the ability to lead workstreams across a small team
  • Communicate clearly, collaborate effectively across organizations, and take ownership of complex design challenges
  • Comfortable providing technical leadership of a small team and driving execution, with the expectation that this role focuses on managing work
  • Strong background in digital design and RTL development (Verilog/System Verilog)
  • Required experience in DDR, PHY, or memory‑related design (a niche domain with a limited talent pool)
  • Experience with complex SoC or IP design and integration
  • Familiarity with synthesis, timing analysis, and end‑to‑end design flows
  • Proven ability to lead technical workstreams or provide technical leadership
  • Experience in Linux‑based development environments; scripting is a plus
  • Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field

Nice To Haves

  • Experience from companies building PHY/DDR IP is strongly preferred (e.g., Intel, Synopsys, Cadence, Qualcomm, Microchip)

Responsibilities

  • Lead microarchitecture definition and RTL implementation of complex IP blocks and subsystems
  • Develop high‑quality RTL and support verification, synthesis, and timing closure
  • Analyze designs for performance, power, and area (PPA) and guide optimization decisions
  • Collaborate closely with architecture, verification, and physical design teams to ensure successful integration
  • Drive technical direction, design reviews, and engineering best practices across a small team
  • Support debug, bring‑up, and silicon validation activities

Benefits

  • AMD benefits at a glance
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