DDR PHY System Design Engineer (San Diego, US)

Qualcomm•San Diego, CA

1d•Onsite

About The Position

QCT mixed-signal IP design team is looking for skilled system architect to help design high-speed, high-performance, and low-power DDR Phys for Qualcomm’s products targeted for 5G, AI/ML, compute, and automotive applications. This role is part of the DDR PHY design team. You’ll help with system design, building, and testing—starting from early ideas all the way to final chip production and validation.

Requirements

5-10 years in DDR PHY system design/architecture
Strong knowledge in JEDEC DDR standards (LPDDR/PCDDR/HBM, etc.) and implication to DDR PHY system design/architecture
Strong knowledge of link-budgets and trainings
Strong communication skills; proven ability to collaborate across global teams
Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.
Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.
PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.

Nice To Haves

Knowledge of signal integrity and power delivery for server products
Knowledge of latest process technology nodes and mixed-signal designs
Solid understanding of design-for-yield and production challenges in high-speed links
Unix/Perl/TCL scripting (must be comfortable with writing scripts)