PHY RTL Design Engineer

Apple • San Diego, CA

10h • Onsite

About The Position

Join Apple’s growing wireless silicon development team, which is responsible for all aspects of wireless silicon development. The team emphasizes highly energy-efficient design and new technologies that enhance user experience, driven by a vertically integrated engineering team covering RF/Analog architecture, Systems/PHY/MAC architecture, VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. This role specifically involves developing signal processing intensive designs for wireless communication SoCs.

Requirements

• Bachelors degree in related field
• Understanding of DSP fundamentals
• Digital Communications knowledge
• Proficiency in RTL Design

Nice To Haves

• Familiarity with UVM DV environment and AI based efficiency improvement flows
• Strong fixed-point knowledge and extensive experience with bit-true cycle-accurate verifications
• Understanding of Decoders - Viterbi, LDPC, Polar
• Understanding of Filter design, multi-radix implementation, and compromises
• Knowledgeable in modern design techniques and energy-efficient/low power logic design, and power analysis
• Familiarity with power estimation (vector-less and vector-based), modeling, profiling, and post-silicon power correlation
• Solid understanding of wireless standards, such as IEEE 802.11, 802.15, Bluetooth or 3GPP is a plus
• Background in computer architecture
• Bus fabric, especially APB/AHB/AXI
• Power management with multiple power domains
• Ability to work well in a team and be productive under ambitious schedules
• Exhibit excellent interpersonal skills and be self-motivated and well-organized
• Experience with FPGA and/or emulation platform desired
• Excellent communication skills – both written, and oral

Responsibilities

• Writing specifications, other documents, and defining Microarchitecture based on MATLAB/C system model
• Architecting area and power
• Efficient low latency designs with scalabilities and flexibilities
• Work with algorithm and software team to ensure performance and power efficiency
• Power and Area efficient RTL logic design, and DV support
• Running tools to ensure lint and CDC/RDC clean design
• Synthesis and timing constraints
• Experience in design of signal processing Wireless protocols

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level