Senior RTL Design Engineer

Baidu USASunnyvale, CA

About The Position

We are seeking a Senior RTL Design Engineer to architect, design, and implement new features, performance improvements, and ISA extensions in RISC-V CPU core generators. This role involves microarchitecture development and specification, ensuring knowledge is shared through excellent documentation and participation in a collaborative design culture. You will perform initial sandbox verification, work with the design verification team on test plans, and collaborate with the physical implementation team to optimize physical design for frequency, area, and power goals. Additionally, you will partner with the performance modeling team for exploration and optimization to meet performance targets.

Requirements

  • 8+ yrs of recent industry experience in high-performance, energy-efficient CPU designs.
  • Expertise in CPU processor designs in one or more of the following areas: instruction fetch and decode; branch prediction; register renaming and instruction scheduling; scalar and/or vector execution units; load-store unit; cache and memory subsystems.
  • Proficiency with hardware (RTL) design in Verilog, System Verilog, or VHDL.
  • Attention to detail and a focus on high-quality design.
  • Ability to work well with others and a belief that engineering is a team sport.
  • Knowledge of at least one object-oriented and/or functional programming language.
  • Background of successful CPU development from architecture through tapeout.
  • MS/ PhD degree in EE, CE, CS or a related technical discipline, or equivalent experience.

Nice To Haves

  • Knowledge of RISC-V architecture is a plus.
  • Experience with Scala and/or Chisel is a plus.

Responsibilities

  • Architect, design and implement new features, performance improvements, and ISA extensions in RISC-V CPU core generators.
  • Microarchitecture development and specification. Ensure that knowledge is shared via great documentation and participation in a culture of collaborative design.
  • Perform initial sandbox verification, and work with design verification team to create and execute thorough verification test plans.
  • Work with physical implementation team to implement and optimize physical design to meet frequency, area, power goals.
  • Collaborate with performance modelling team for performance exploration and optimization to meet performance goals.
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