RTL Power Management Engineer

Advanced Micro Devices, Inc•San Jose, CA

About The Position

The focus of this role is to plan, build, and execute the verification of new and existing features for AMD’s graphics processor IP, resulting in no bugs in the final design. You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/time zones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.

Requirements

Bachelors or Masters degree in computer engineering/Electrical Engineering

Nice To Haves

Strong front-end RTL engineering background
Expertise with low-power design methodologies and trade-offs.
Hands-on expertise with EDA tools such as PrimeTime, PrimePower, Power Artist.
Experience designing with multiple power domains and islands using UPF.
Strong communication skills, able to summarize complex problems for executives as well as drill down to details with architects and engineers
Strong analytic and problem solving skills including the ability to analyze current behavior, identify potential areas for improvement, and design of experiments
Experience with Arm architecture and APB, AXI, CHI protocols
Experience with design reuse, including RTL, constraints, and waivers
Experience with SoC level design integration
Experience with automation using scripting techniques such as PERL, Python, or Tcl
Experience with timing constraints and timing exceptions
Experience running standard quality checks such as LINT and CDC
Experience designing with multiple power domains including writing UPF
Must be a self-starter and self-motivated

Responsibilities

Own the design and implementation of blocks to meet functional, timing, area and power requirements
Guide and review verification for these blocks
Design and implement logic functions that enable efficient test and debug
Implement automation to increase design team efficiency
Perform vector-based and vector-less power estimation for different use case scenarios and analyze results to identify areas for improvement.
Drive static and dynamic power analysis and optimization for complex SoCs and IP blocks.
Drive low-power design strategies.
Power domain/island creation (with UPF).
Develop and maintain power analysis flows using industry-standard EDA tools and emerging, cutting-edge methodologies.
Correlate RTL power estimates with gate-level and post-layout power results.