RTL Design Engineer

Delos Data Inc • Palo Alto, CA

19h • Hybrid

About The Position

We are a stealth-mode startup building foundational technology to address performance, scalability, and resiliency challenges in large-scale AI data center clusters. We are backed by top-tier VC firms and notable angel investors. The company is led by experienced builders and operators who have founded companies, taken them to scale, and exited successfully. We work with a strong sense of unity and shared responsibility, and we expect trust, integrity, and respect in how we collaborate and make decisions. We hold ourselves accountable to one another and to the quality of the work we deliver. Headquartered in Silicon Valley, we operate across a mix of remote and on-site locations in the U.S. and Canada. We aim to create an environment where people are treated fairly, supported in their growth, and are empowered to do meaningful work alongside others who take the craft seriously.

Requirements

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field
• 5+ years of experience in RTL design
• Strong hands-on experience with Verilog/SystemVerilog
• Solid understanding of synchronous digital design and microarchitecture principles
• Experience with simulation and debug tools (e.g., VCS, Questa, Verdi, DVE)
• Familiarity with synthesis, timing, and physical design constraints
• Strong analytical and problem-solving skills
• Clear written and verbal communication skills for cross-functional collaboration
• High attention to detail and ability to deliver high-quality design outcomes
• Ability to work independently and manage tasks to completion

Nice To Haves

• Experience designing high-performance systems (e.g., AI/ML accelerators, networking, or SoCs)
• Familiarity with low-power design techniques (clock gating, power gating)
• Exposure to DFT concepts and design-for-test considerations
• Experience with scripting (Python, Tcl, or similar)
• Experience working in advanced semiconductor process nodes

Responsibilities

• Design and implement RTL for complex digital subsystems using Verilog/SystemVerilog
• Translate architectural specifications into clean, efficient, and scalable microarchitectures
• Collaborate with architecture, verification, and physical design teams to ensure design correctness and closure
• Develop high-quality, reusable RTL with strong coding standards and documentation
• Perform linting, CDC analysis, and ensure synthesis readiness of designs
• Support integration and debug of RTL in simulation and early silicon environments
• Participate in design reviews and provide technical input on architecture and implementation tradeoffs
• Work with verification teams to ensure comprehensive functional coverage
• Assist in timing closure and support backend teams as needed
• Contribute to continuous improvement of design methodologies, flows, and tools

Benefits

• meaningful equity
• benefits
• 401(k)

What This Job Offers

• Job Type: Full-time
• Career Level: Senior