Staff / Sr Staff RTL Design Engineer

Alphawave Semi•Toronto, ON

3d•Hybrid

About The Position

Alphawave Semi is looking for experienced SoC RTL design engineers to contribute to their next generation connectivity networking products. This role offers an incredible opportunity to be part of the AI revolution and contribute to the complete semiconductor development cycle, from concept to product. The ideal candidate will have a strong and extensive background in RTL design across multiple projects. As an experienced RTL Design Engineer, you will work in SoC design and SOC-Subsystem design. You will be responsible for microarchitecture/RTL coding of the SOC/subsystems and create microarchitecture documents. You will work with verification teams on achieving the code & functional coverage. You will work with Physical design team to meet area, power and performance goals. You will support physical design teams, verification teams, software teams and FPGA teams to ensure high quality SoC and ensure successful tapeout.

Requirements

Strong background with multi-year and multi-project experience in RTL SoC Design (Verilog/VHDL), and ASIC/FPGA debug methodologies
Proficient in reviewing high-level test plans and coverage metrics.
Expertise in Design Compiler Synthesis and formal verification using LEC.
Comprehensive understanding of timing closure.
Experience in post-silicon bring-up and debugging.
Team player with strong communication skills to ensure effective program execution.

Nice To Haves

Experience in SerDes PHY, DSP, and Analog mixed signal is desirable
Knowledge in Ethernet and PCIe standards is desirable
Ability to develop architecture and micro-architecture based on specifications.
Knowledge of bus protocols such as AHB, AXI, and peripherals like PCIe, USB, Ethernet, etc.
Experience with memory controller designs and microprocessors is an advantage.
Knowledge of chip IO design and packaging is beneficial.

Responsibilities

Micro architect and RTL Design of SoC SubSystem/IP blocks
Develop UPF and run CLP checks
Responsible for RTL quality checks - Lint/CDC/LEC
Create appropriate documentation for hardware blocks
Responsible for analyse / debug / fixing issues reported by verification team
Develop the synthesis constraints for the blocks / subsystem
Work with SOC Architect/Leads to integrate the design, review/sign-off verification plan, DFT and PD implementation