Memory Architect

Normal Computing Corporation•Palo Alto, CA

13d

About The Position

Normal Computing is building AI inference hardware based on its Thermo In-Memory Computing architecture. The Memory Architect will translate these concepts into silicon and lead the design of memory elements, read/write paths, memory-array organization, and microarchitecture that integrates memory operations with high-performance compute. The role is accountable for delivering substantial performance improvements in AI inference. Reporting to the Director of Silicon Engineering, the Memory Architect will work with scientists, microarchitects, physical design engineers, and analog design engineers to implement a standard-cell library combining digital compute primitives with ThermoDRAM compute primitives, and to develop a high-performance Compute In-Memory System. The role owns technical relationships with major manufacturers from PDK acquisition through test-chip tapeout and production silicon. Normal Computing is an applied AI company developing foundational hardware and software for the semiconductor industry and AI infrastructure. Its team works across New York City, Mountain View, London, Copenhagen, and Seoul.

Requirements

Substantial experience in memory architecture or circuit design at a memory manufacturer or memory-centric compute company.
Deep understanding of memory-array physics, including 1T/3T/6T/8T SRAM cells, DRAM bitcells, capacitance, sensing, read/write operations, core timing, retention, and reliability.
Hands-on experience with embedded memory or random access memory technology and PDKs, including developing memory test chips through tapeout.
Ability to move between SPICE-level circuit behavior and architecture-level performance and power models.
Strong fundamentals in at least one programming language, such as Python, C, or C++, for modeling and performance prediction.
Experience with RTL and SystemVerilog to model and optimize dataflow and specify compute-block requirements.
Experience with different interface types, including memory interfaces.
Excellent written and spoken communication skills.

Nice To Haves

Experience with processing-in-memory or near-memory compute.
Experience with non-volatile memory technology.
Experience with DRAM technology, including eDRAM.
Major publications at ISSCC, VLSI, IEDM, ISCA, or other major conferences.
Existing relationships with manufacturers.

Responsibilities

Define memory requirements and floorplans that enable in-memory compute, including read/write paths to ALUs and novel memory primitives.
Specify read/write circuitry and row and column decoders for novel memory and in-memory compute operations.
Architect local and global datapaths, segmented buses, and on-die fabrics that move data between memory arrays and logic.
Own power distribution, power budgets, thermal limits, redundancy, and ECC to support performance while protecting retention and yield.
Own access to process design kits and design rules, and assess the architectural modifications supported by existing design rules.
Drive the tapeout plan, including an upcoming shuttle, test-chip content, schedule, and bring-up.
Partner with analog engineers developing and characterizing the primitive device library, including write circuits, drivers, and multiplexers; set requirements and ensure design choices support architectural performance.
Define interfaces between the custom memory product and external hosts, including SERDES, PCIE, Ethernet, DDR5, LP6, or HBM-class interfaces, command-set extensions, and related controller and timing implications.
Oversee development of SPICE, analytical, and cycle-level models for performance, power, and yield.
Partner with performance and machine learning engineers to validate that projected PPA improvements translate into workload-level gains.
Own technical relationships with major manufacturers from PDK acquisition through tapeout of test chips and production silicon.