# AI/ML Silicon Accelerator Memory Architect

Broadcom • San Jose, CA

20h

About The Position

The Principal Architect/Distinguished Architect will define the end-to-end memory and data transport architecture for AI/ML accelerators, spanning memory technology, controllers, on-die networks, DMA engines, and scratchpads that feed compute blocks. The role owns the complete data path across multiple silicon generations and makes performance-versus-power trade-offs in collaboration with internal teams and external memory and IP vendors.

The architect will establish a multi-generation memory strategy across HBM, LPDDR, GDDR, DDR, on-die SRAM hierarchies, and scratchpads. They will derive capacity, bandwidth, and latency requirements from AI workloads, including model size, KV-cache growth, prefill versus decode, and MoE sparsity. The role also covers memory controller and cache/scratchpad microarchitecture, including scheduling, address mapping, and QoS for compute, DMA, and host traffic.

The position owns energy-efficient data movement from memory to MACs, including on-die interconnect topology, flow control, deadlock avoidance, QoS under mixed traffic, and DMA, gather/scatter, layout-transform, and multicast engines. The pJ/bit budget is a first-class constraint. The architect will develop analytical and simulation-based models to support architectural decisions with quantified confidence.

Requirements

• MSEE/MSCE or PhD in EE, CE, CS, or a related field, or equivalent demonstrated architectural impact.
• 18+ years in ASIC/SoC architecture focused on memory systems and data movement for HPC or AI.
• Deep knowledge of HBM, DDR/LPDDR/GDDR, memory controller architecture, cache coherency and memory consistency models, and tiered and pooled memory.
• Demonstrated ownership of a data movement architecture covering on-die interconnect, DMA/copy engines, buffer hierarchies, and the dataflow connecting them to compute.
• Knowledge of the latency, area, and power costs of NVLink, UALink, RDMA, ARM CHI, UCIe, and PCIe protocols.
• Strong performance modeling and system-level simulation background.
• First-principles command of latency, throughput, utilization, and scalability.

Responsibilities

• Define end-to-end memory and data transport architecture for AI/ML accelerators across multiple silicon generations.
• Develop the portfolio's multi-generation memory strategy for HBM, LPDDR, GDDR, DDR, on-die SRAM hierarchies, and scratchpads.
• Derive memory capacity, bandwidth, and latency requirements from AI workloads, including model size, KV-cache growth, prefill versus decode, and MoE sparsity.
• Architect memory controllers and cache/scratchpad microarchitecture, including scheduling, address mapping, and QoS across compute, DMA, and host traffic.
• Own data transport from memory to MACs, including on-die interconnect topology, flow control, deadlock avoidance, and QoS under mixed traffic.
• Architect DMA, gather/scatter, layout-transform, and multicast engines for efficient data movement.
• Manage the pJ/bit budget as a primary architectural constraint.
• Develop analytical and simulation-based models to support architectural decisions with quantified confidence.
• Make performance-versus-power trade-offs and co-architect with internal teams and external memory/IP vendors.

Benefits

• Discretionary annual bonus
• Competitive new-hire equity grant and annual equity awards
• Medical, dental, and vision plans
• 401(k) participation with company matching
• Employee Stock Purchase Program (ESPP)
• Employee Assistance Program (EAP)
• Company-paid holidays
• Paid sick leave and vacation time
• Paid Family Leave and other leaves of absence in accordance with applicable laws

What This Job Offers

• Job Type: Full-time
• Career Level: Principal