Manager, Digital Design - Mixed-Signal High-Speed I/O SerDes
About The Position
Lead a team in NVIDIA’s Mixed-Signal High-Speed I/O SerDes group, developing technology that supports gaming, artificial intelligence, deep learning, and autonomous driving. The team’s designs serve standard and proprietary high-speed protocols as key IP in sophisticated SoCs. The role collaborates with analog designers, system architects, and other engineering teams to deliver high-performance solutions and drive innovation. The manager leads mixed-signal chip development, from algorithm planning and specification through digital design, verification, front-end flows, and coordination with back-end teams for chip tape-outs. The position also leads silicon bring-up and performance optimization, aligns technology roadmaps with business objectives, and establishes standard methodologies for mixed-signal design and verification.
Requirements
- M.S. or Ph.D. in Electrical Engineering, or equivalent experience.
- Over 8 years of overall experience in mixed signal.
- Proven experience in mixed-signal chip design, including 3 or more years in a leadership role.
- Expertise in Verilog or SystemVerilog, logic design, and circuit modeling in RTL for mixed-signal blocks.
- Strong background in custom digital circuit design and adaptation algorithms such as FFE, DFE, CTLE, CDR, and offset cancellation.
- Understanding of high-speed SerDes I/O digital design and knowledge of protocols such as Ethernet and PCIe.
- Experience with industry-standard verification methodologies such as UVM.
- Proficiency with static timing and formal verification tools.
- Excellent communication and leadership skills, with the ability to drive technical strategy.
Responsibilities
- Lead and mentor a team of engineers developing mixed-signal chips.
- Supervise planning and specification of algorithms and evaluation of power, performance, and area (PPA) trade-offs.
- Guide the design of digital circuits, including filters and analog calibration circuits.
- Ensure verification of digital designs using direct and random testing methodologies.
- Lead front-end design flows, including Lint, CDC, synthesis, DFT, LEC, and STA, and coordinate with back-end teams for chip tape-outs.
- Drive silicon bring-up efforts and performance optimization.
- Collaborate with multifunctional teams to align technology roadmaps with business objectives.
- Establish and maintain standard methodologies for mixed-signal design and verification.
Benefits
- Equity
- Benefits
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What This Job Offers
Job Type
Full-time
Career Level
Manager
