Principal Engineer

Broadcom • San Jose, CA

1d

About The Position

Broadcom Core Switching Group (CSG) is seeking a Logic Design Engineer focused on Packet Processing for our high performance Ethernet switch chip. In this position, you would be joining an innovative team that designs and builds the hardware, software and networking technologies that power the infrastructure of the leading data centers in the world. The Core Switch Group (CSG) at Broadcom focused on developing high-performance Ethernet switch silicon and software, primarily targeting hyperscale data centers, cloud providers, and enterprise networks. Our group is recognized as an industry leader in merchant silicon, enabling massive network bandwidth for AI infrastructure and cloud applications. Our organization works on all levels of ASIC development, spanning high-level architecture, to RTL design and verification and volume manufacturing. We are looking for a motivated and astute individual to join our team as a Logic Design Engineer. As a Logic Design Engineer you will use your knowledge of specifications, mathematics, and computation to write efficient and elegant RTL for implementing components of complex networking ASICs. This role requires participation through the full program lifecycle: developing micro-architecture specifications, RTL implementation, unit verification, timing convergence, ECO implementation, debug analysis and reviews.

Requirements

• B.S. in Electrical Engineering, Computer Engineering, Computer Science, or equivalent.
• B.S. with 8 years of experience, or M.S. with 6 years of experience in digital design on multiple networking ASICs.
• 4+ years of experience in Verilog based RTL design or verification, in deep submicron technologies.
• Familiarity with Ethernet and other networking protocols.

Nice To Haves

• Extensive experience with Ethernet, TCP/IP, MPLS, tunneling and other networking protocols.
• Extensive experience with packet processing architectures packet parsing, ACLs, metering, policing, etc.
• Experience achieving timing closure on high performance ASICs, in deep submicron technologies.
• Experience with low power design techniques, power estimation methods, clock domain crossing techniques.
• Experience with scripting languages, such as Python or Perl.

Responsibilities

• Developing micro-architecture specifications
• RTL implementation
• Unit verification
• Timing convergence
• ECO implementation
• Debug analysis and reviews

Benefits

• Medical, dental and vision plans
• 401(K) participation including company matching
• Employee Stock Purchase Program (ESPP)
• Employee Assistance Program (EAP)
• company paid holidays
• paid sick leave and vacation time
• Paid Family Leave and other leaves of absence

What This Job Offers

• Job Type: Full-time
• Career Level: Principal
• Number of Employees: 5,001-10,000 employees