Intern, Photonic Device Design

Ayar Labs•San Jose, CA
•Onsite

About The Position

Ayar Labs is hiring an Intern, Photonic Device Design for a term running from May to August 2027. The position is on-site at the company’s San Jose office. The intern will apply knowledge of photonic device physics to improve the bandwidth density, energy efficiency, and manufacturability of Ayar Labs’ co-packaged optics platform. The work involves taking device designs from simulation to silicon on a leading-edge process, then using hardware measurements to refine models and improve devices for a subsequent submission. Ayar Labs develops optical I/O chiplets and co-packaged optics, using silicon photonics to move data for AI compute hardware. The company does not provide immigration support, except for F-1 status, or relocation support for this position. The posting expires upon reaching its application threshold.

Requirements

  • Solid understanding of photonic device physics, including waveguides, couplers, gratings, and micro-ring resonators.
  • Experience with simulation tools for passive optical devices, such as FDTD and mode solvers.
  • Python skills and experience writing structured code in a team environment.
  • Ability to connect simulation to measurement by designing, characterizing, and iterating on device performance.
  • Familiarity with optical transceiver principles and co-packaged optics architectures.
  • Demonstrated use of AI tools to achieve meaningful productivity gains in design or analysis workflows, such as device optimization or AI-assisted code development.
  • Actively pursuing a Master’s or PhD in Electrical Engineering or another engineering discipline with a photonics specialization.

Responsibilities

  • Apply photonic device physics knowledge to improve bandwidth density, energy efficiency, and manufacturability of the co-packaged optics platform.
  • Take device designs from simulation to silicon on a leading-edge process.
  • Connect simulations to measurements by designing, characterizing, and iterating on device performance.
  • Use hardware results to refine models and develop improved devices for the next submission.
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