Senior Principal Engineer, Device Design

Intel Corporation•Santa Clara, CA

1d•$265,480 - $374,800•Hybrid

About The Position

Intel’s Manufacturing Development and Customer Engineering (MDCE) organization supports the company’s transformation into a global foundry service provider, with a focus on technology customization, yield improvement, performance optimization, and customer delivery. The Senior Principal Device Design Engineer provides strategic technical leadership for the architecture, definition, and optimization of next-generation and high-volume manufacturing semiconductor technologies. The role applies deep semiconductor device-physics expertise to set technical roadmaps and performance direction across advanced logic, SRAM, low-power mobile, analog, and mixed-signal applications. The engineer serves as a primary technical bridge among Process Integration, Yield, Module Engineering, and product partners. The role establishes technical direction and target validations, and ensures silicon-to-simulation accuracy across Intel’s technology portfolio. It also engages external customers and product design teams, directs technology customization and design-rule governance, evaluates electrical test and yield data, and mentors engineers and researchers. This is an experienced-hire role eligible for Intel’s hybrid work model, allowing time to be split between an assigned Intel site and off-site work. The posting lists Hillsboro, Oregon, as the primary location, with additional locations in Phoenix, Arizona, and Santa Clara, California. It is a Position of Trust and requires consent to and passage of an extended background investigation.

Requirements

Progressive semiconductor-industry experience focused on CMOS device physics, device design, and semiconductor technology development.
Demonstrated technical leadership, including leading cross-functional teams to define, develop, and deliver advanced semiconductor technologies and design rules into high-volume manufacturing.
Deep proficiency in design-rule development, validation, and waiver management, and understanding of how layout constraints affect product yield.
Proven expertise in statistical data analysis, Design of Experiments (DOE), and interpretation of test-chip, electrical-test, and yield trends.
Master’s degree in Electrical Engineering, Physics, Material Science, or a related field.
At least 15 years of relevant semiconductor device and technology development experience.

Nice To Haves

PhD in a related field.
Architectural experience in advanced-node transistor design and scaling.
Deep experience customizing semiconductor technologies for low-power, analog, mixed-signal, and memory applications.
High-level familiarity with physical-verification flows, Design Rule Checker (DRC) development, and mask-generation concepts.
Extensive experience in a high-volume manufacturing environment focused on statistical process control (SPC) and yield monitoring.
Exceptional verbal and written communication skills, including the ability to influence executive stakeholders and guide collaborative partners through complex technical trade-offs.

Responsibilities

Lead cross-functional, multidisciplinary teams in defining base and derivative semiconductor architectures, including advanced transistors, interconnects, and design rules for logic, low-power, memory, analog, and mixed-signal applications.
Partner with external customers, product design teams, and internal engineering groups to understand product requirements and resolve circuit-level performance, reliability, and leakage trade-offs.
Translate product needs into tailored silicon solutions.
Drive development and implementation of customized semiconductor features across logic and memory technologies, integrating them with existing manufacturing processes and platforms.
Set and govern device and interconnect performance targets, and evaluate silicon-to-simulation health, model readiness, and design feasibility for high-volume manufacturing.
Bridge Process Integration, Process Module, Device Physics, Yield Engineering, and Product Design to coordinate technology handoffs and resolve system-level constraints.
Direct validation and strategic waiver management for advanced design rules, balancing manufacturing compliance and yield with product design flexibility.
Guide evaluation of electrical test and yield data using statistical methods and data analysis to turn experimental silicon data into process and design intelligence.
Mentor engineers and researchers, monitor emerging semiconductor industry trends, and foster technical excellence and customer-centric innovation.