Senior Principal Analog Design Engineer

onsemi•Allen, TX

About The Position

onsemi is seeking an Analog Design Engineer to contribute to the development of power management and clocking analog IP blocks for Treo-based SoC platforms. The role is a hands-on individual contributor position reporting to the Analog Design Team Manager. It is responsible for the detailed design, verification, and delivery of high-quality analog IP, working with cross-functional partners to support product tape-out and silicon validation. The Treo Platform is an analog and mixed-signal solution built on 65nm BCD technology, supporting voltage ranges from 1–90V and operating temperatures up to 175°C. It serves automotive, medical, industrial, and AI data-center applications. Products are manufactured at onsemi's 300mm fab in East Fishkill, New York. The engineer will contribute to IP architecture, execute design and verification, integrate validated analog blocks into SoC subsystems, support lab bring-up and silicon debug, and document work for IP reuse and platform quality. The role also involves design sign-off analyses and applying scripting or automation to improve productivity and robustness.

Requirements

10+ years of experience in analog IC design.
Hands-on experience designing power management and/or clocking circuits for integrated SoCs.
Solid understanding of device physics, analog architectures, and layout-dependent effects.
Proficiency with SPICE/AMS simulation, variability analysis, and mixed-signal co-simulation.
Ability to work independently on assigned blocks while clearly communicating progress and risks.

Nice To Haves

Experience with Verilog-A/AMS/SV RNM modeling or mixed-signal verification environments.
Exposure to automotive or industrial reliability and functional-safety requirements.
Interest in AI/ML-assisted design, automation, or design-space exploration.

Responsibilities

Design, simulate, and verify power management IP, including LDOs, DC/DC converters, and charge pumps.
Design and implement clocking circuits, including PLLs, DLLs, oscillators, and clock distribution networks.
Contribute analysis, trade-off studies, and design proposals to support IP architecture definition.
Execute schematic design, provide layout guidance, perform post-layout extraction, and run corner and Monte Carlo analyses to meet specifications.
Deliver validated analog blocks into mixed-signal and digital-on-top subsystems for SoC integration.
Collaborate with digital design, verification, PDK/technology, and validation teams to resolve integration issues.
Participate in lab bring-up, silicon characterization, and post-silicon debug with validation and test engineers.
Document designs, assumptions, and test results to support IP reuse and long-term platform quality.
Use industry-standard schematic capture and SPICE/AMS simulation tools.
Perform PVT, noise, jitter, reliability, EM/IR, and aging analyses as part of design sign-off.
Follow established design methodologies, review checklists, and quality metrics, and suggest incremental improvements.
Apply scripting, automation, or data-driven techniques to improve design productivity and robustness.
Collaborate with peers and CAD teams to evaluate emerging EDA capabilities, including AI-assisted design workflows.