MTS, Interface Pathfinding Hardware Development Engineer

Micron • Boise, ID

13d

About The Position

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence. The Interface Pathfinding team drives performance-scaling innovation across circuits, signaling, packaging, and interconnects with a 3–5 year technology horizon. As the Interface Pathfinding Hardware Development Engineer, you will own characterization for a high-speed interface test-chip program. This includes the characterization plan and its success criteria, development of the characterization bench hardware and its automation, the measurement-uncertainty budget, and the correlation report proving the silicon matches the models. You will join a small, senior team spanning analog design, layout, digital design, and verification, working closely with the Chip Lead and the Signal Integrity and Physical Design engineers. This is a foundational hire for a growing program, with strong execution early expected to lead to follow-on projects of increasing scope, team size, and characterization complexity, including an expanding mandate for AI-enabled engineering leadership across the organization.

Requirements

• MSEE with 10+ years (or BSEE with 12+ years) in semiconductor characterization or test engineering, including at least one program owned from plan through sign-off
• High-speed time-domain measurement including Rj/Dj separation and jitter transfer at multi-GT/s rates
• BERT and pattern generator/analyzer operation for link margining; switch-matrix automation with per-path de-skew
• Root Cause and Corrective Action through Principal Component Analysis and First-Principles Design of Experiments
• Instrument automation for characterization across corners and conditions
• PDN and load-transient measurement; judgment on bench reference-clock and supply-noise realism
• Development of simulation plans to pre-validate a test approach; design-of-experiments applied to characterization and root cause
• First silicon bring-up of an internally designed device
• Frequency-domain fixture de-embedding (VNA S-parameters, 2x-thru or TRL, TDR) correlated to field-solver models
• Technical representation of the engineering organization to customers or vendors
• Cross-organizational technical leadership: demonstrated track record of developing methodologies, tools, or frameworks adopted by engineering teams beyond the immediate program
• Agentic AI workflow construction and deployment including analysis, development, and automation

Nice To Haves

• Pro-active, visionary, and collaborative, with clear written and verbal communication of complex technical issues
• Familiarity with silicon photonics and optical measurement techniques
• BER-bathtub extrapolation and eye-mask methodology; CTLE/DFE equalization effects on measured margin
• On-die calibration verification; on-die PDN impedance correlated to power-integrity simulation
• Split-lot process-corner characterization correlated to STA corners
• JEDEC or external-forum participation; technical presentation record

Responsibilities

• Derive the electrical characterization plan from the architecture specification and SI link budget before RTL freeze, with each test case traceable to a specification parameter and success criteria.
• Author observability and test-access requirements (debug registers, trim exposure, loopback and pattern modes, analog test-mux) into the register map before RTL freeze.
• Develop and own the characterization architecture from hardware and test board specifications through to the automated data acquisition framework.
• Measure, calibrate, and de-embed characterization hardware to isolate device performance from measurement noise.
• Serve as the program’s expert across link and timing integrity, power delivery, I/O-ring robustness, environmental corners, and first-silicon bring-up.
• Co-author the per-revision sim-to-silicon correlation report with the SI engineer and lead the debug tiger team when silicon deviates from simulation.
• Sign the characterization-readiness items on the tape-out checklist, then author the post-silicon characterization report and the correlation-gap table for the next test chip.
• Define bench capability against target data rates, represent findings to vendors, standards forums, and management, mentor junior engineers, and contribute to the IP portfolio.
• Serve as the Interface Pathfinding organization’s primary resource for agentic-AI workflow design and deployment.
• Architect, implement, and document AI-assisted development and characterization pipelines — including characterization plan generation, data analytics, and predictive modeling via sim-to-silicon correlation acceleration.
• Represent Micron’s AI-enabled characterization methodology to external partners, standards bodies, and internal leadership.

Benefits

• Choice of medical, dental and vision plans
• Benefit programs that help protect your income if you are unable to work due to illness or injury
• Paid family leave
• Robust paid time-off program
• Paid holidays

What This Job Offers

• Job Type: Full-time
• Career Level: Senior