Sort Interface Pathfinding and Development Engineer

Intel•Hillsboro, OR

12d•Onsite

About The Position

Intel Corporation is one of the world's leading semiconductor companies, driving innovation across computing, connectivity, and artificial intelligence. With a bold vision to shape the future of technology, Intel is transforming how the world processes, stores, and communicates data. Our Advanced Packaging ,Test and Manufacturing (APTM) organization is at the forefront of this transformation, delivering industry-leading packaging and test technologies that power products across Client, Data Center, AI, Networking, and External Foundry markets. At Intel, we believe the next big thing starts with you. We are seeking a talented and driven Sort Interface Pathfinding and Development Engineer to join our Sort Interface Development team in Oregon. In this high-impact role, you will pioneer breakthrough silicon interface probing & test solutions that enable best-in-class die and wafer sort capabilities across leading-edge process nodes and advanced heterogeneous packaging platforms — including EMIB, EMIB-T, Foveros, and Foveros Direct. As Intel scales its Open System Foundry and OSAT (Outsourced Semiconductor Assembly and Test) business model, you will play an instrumental role in establishing world-class, customer-ready sort interface capabilities. You will lead electro-mechanical pathfinding, test hardware development, customer and supplier technical co-design, and probing process qualification to support both Intel's internal product roadmap and external Foundry customers.

Requirements

Bachelor’s degree in electrical engineering, Mechanical Engineering, Materials Science, or a related STEM field with 6+ years of industry experience OR Master's degree in the same fields with 4+ years of industry experience OR Ph.D. in the same fields with 2+ year of relevant post-graduate or industry experience
Experience with wafer/die sort Technology , prober-tester cell integration, and qualification of advanced probe card technologies
Structure and execute DOEs to evaluate probing margins, yield, and process health
Direct experience in ATE test hardware/methodology, Sort/Class product development, or PCB/space transformer/substrate design rules and stackup architectures

Nice To Haves

6+ years of experience in: Advanced probing process characterization
Direct experience managing technical relationships with external probe card/substrate suppliers or providing test hardware application support to external foundry/OSAT customers
Knowledge of OSAT/Foundry test operations, multi-client test cell standards, customer design collateral/PDK enablement, or turnkey test delivery models
Experience qualifying probe technologies for fine-pitch micro-bumps, 2.5D/3D architectures (EMIB, EMIB-T, silicon bridges), or wafer-level chip-scale probing
Hands-on experience with commercial ATE platforms such as Advantest V93k or Teradyne Ultra-FLEX

Responsibilities

Formulate and execute rigorous Design of Experiments (DOE) to optimize and qualify next-generation probing technologies and contact architectures for wafer and die sort operations
Serve as the lead technical liaison for Foundry and OSAT customers, translating complex chiplet and package requirements into scalable sort interface specifications
Author industry-standard sort design rules and Interface Design Kits (IDKs) to streamline ecosystem integration for external fabless customers and design partners
Collaborate with customer design and DFT teams to architect test interface hardware, resolve technical gaps, and synchronize testability roadmaps
Partner with global Test Solution vendors and PCB suppliers to pioneer state-of-the-art probing capabilities
Direct supplier and pathfinding initiatives to align vendor roadmaps with internal efficiency and performance goals
Drive supplier accountability and manufacturing readiness to guarantee on-time hardware delivery for critical New Product Introductions (NPI)