Integrated Circuit Design Verification Engineer
About The Position
Snap Inc. is seeking an Integrated Circuit Design Verification Engineer to join the Spectacles Team at Snap Inc. The role is part of a multidisciplinary team designing display integrated circuits for augmented reality and involves close collaboration with digital design, analog logic, software, and verification engineers. The engineer will develop and implement UVM-based and assertion-based testbenches, create and execute verification test plans that include functional and code coverage, use the Siemens Questa tool set for verification and debugging, and specify and configure tools and automation. The position follows Snap’s “Default Together” policy, which expects team members to work in an office four or more days per week. The position is eligible for equity in the form of RSUs. In the United States, the annual base salary range depends on the assigned pay zone: $173,000–$259,000 in Zone A (CA, WA, NYC), $164,000–$246,000 in Zone B, and $147,000–$220,000 in Zone C.
Requirements
- BSEE, MSEE, or relevant years of experience.
- 10 or more years of experience in ASIC design verification.
- Strong knowledge of UVM and SystemVerilog for advanced verification methodologies.
- Strong knowledge of digital functional simulation and tools such as Siemens Questa.
- Strong knowledge of good Verilog RTL coding practices.
- Scripting and automation experience, such as TCL, Make, Perl, Python, and Shell scripts in a Linux environment.
- Excellent written and verbal English communication.
Nice To Haves
- Experience with the entire verification process, from planning to sign-off.
- Experience with Siemens’ UVM Framework.
- Experience in emulation.
- Experience in RTL design.
- Familiarity with video and display systems, MIPI, AMBA, I2C, SPI protocols, and embedded microcontrollers.
- Familiarity with ASIC test or production flow.
- Ability to take initiative, organize complex issues, and drive them to closure.
- Ability to multitask and prioritize.
Responsibilities
- Work as part of a multidisciplinary team designing display integrated circuits for augmented reality.
- Collaborate closely with digital design, analog logic, software, and verification engineers.
- Develop and implement UVM-based and assertion-based testbenches.
- Create and execute verification test plans, including functional coverage and code coverage.
- Use the Siemens Questa tool set for verification and debugging tasks.
- Specify and configure tools and create automation.
Benefits
- Paid parental leave
- Comprehensive medical coverage
- Emotional and mental health support programs
- Compensation packages that include the opportunity to share in Snap’s long-term success
- Equity in the form of RSUs
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What This Job Offers
Job Type
Full-time
Career Level
Senior
