Integrated Circuit Backend/Physical Design Engineer

Battelle • Columbus, OH

7d • Hybrid

About The Position

Battelle's Advanced Microsystem Solutions Business Line develops advanced integrated circuit technologies and hardware assurance solutions for government and commercial customers. We are seeking a Backend/Physical Design Engineer to support implementation and signoff of advanced digital integrated circuits and systems-on-chip (SoCs) in our Columbus, Ohio location. The successful candidate will be responsible for physical design implementation, timing closure, power optimization, physical verification, and tape-out activities across advanced semiconductor technologies. The ideal candidate will have experience with industry-standard backend design tools, static timing analysis, signal integrity analysis, and physical design methodologies. This role offers the opportunity to contribute to cutting-edge microelectronics programs focused on secure and high-performance computing technologies while collaborating closely with RTL design, verification, foundry, and technology teams.

Requirements

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field
• 3+ years of physical design experience
• Strong experience in physical design flow (floor planning, placement, clock tree synthesis, routing, optimization)
• Expertise in static timing analysis (STA) and timing closure techniques
• Knowledge of power analysis and power optimization methodologies
• Experience with signal integrity, IR drop analysis, and EM/electromigration analysis
• Proficiency with physical verification (DRC, LVS, antenna, ERC)
• Hands-on experience with industry-standard backend EDA tools (Cadence Innovus)
• Scripting skills (TCL, Python) for automation and flow development
• Understanding of process technology nodes and design rules
• Knowledge of clock domain crossing (CDC) and timing constraints
• Familiarity with standard cell libraries and design kits
• Knowledge of Version Control (Git)
• Must be a US citizen and able to obtain and maintain US Government security clearance

Nice To Haves

• Experience with advanced technology nodes
• Experience with ASIC subsystem integration, top-level assembly, IO ring development, manual layout, and coordination of physical implementation activities through signoff and tapeout.
• Low power design techniques (power gating, multi-voltage, retention)
• FinFET or Gate-All-Around (GAA) technology experience
• High-speed design and advanced packaging knowledge
• Multi-corner multi-mode (MCMM) timing analysis
• Experience with 3D IC or chiplet design
• Knowledge of extraction tools and parasitic analysis
• Design for Manufacturing (DFM) and Design for Yield (DFY) techniques
• Understanding of thermal analysis and heat dissipation
• Familiarity with advanced packaging (2.5D, 3D, chiplet integration)
• Experience with assured microelectronics and hardware security principles (cryptography, side-channel, fault injection, radiation tolerance, hardware CWEs, etc.)
• Active Secret or Top-Secret security clearance

Responsibilities

• Execute physical design implementation from netlist to GDSII
• Perform floor planning, power planning, and pin placement
• Conduct placement optimization and clock tree synthesis (CTS)
• Perform detailed routing and optimization for timing, power, and area
• Achieve timing closure across corners and modes
• Conduct power analysis and implement power reduction techniques
• Perform signal integrity analysis and resolve SI/IR drop violations
• Execute physical verification checks (DRC, LVS, antenna, ERC)
• Generate timing constraints and perform static timing analysis
• Collaborate with front-end design and verification teams
• Work with foundry and technology teams on design rule compliance
• Create and maintain physical design documentation and reports
• Develop and improve physical design methodologies and flows
• Support signoff activities and tape-out preparations
• Debug and resolve design issues found during physical verification

Benefits

• Compressed work schedule
• Hybrid work arrangement
• Paid time off
• Medical coverage
• Dental coverage
• Vision coverage
• Wellness incentives
• Optional supplemental benefits
• Coverage for partners
• Gender-affirming care and health support
• Family formation support
• 401(k) retirement savings plan
• Tuition assistance

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level