Integrated Circuit Backend/Physical Design Engineer

Battelle • Columbus, OH

6d • $86,400 - $123,100 • Hybrid

About The Position

Battelle’s Advanced Microsystem Solutions Business Line develops advanced integrated circuit technologies and hardware assurance solutions for government and commercial customers. The Backend/Physical Design Engineer will support implementation and signoff of advanced digital integrated circuits and systems-on-chip (SoCs) at Battelle’s Columbus, Ohio location.

The role is responsible for physical design implementation, timing closure, power optimization, physical verification, and tape-out activities across advanced semiconductor technologies. The engineer will use industry-standard backend design tools and work with static timing analysis, signal integrity analysis, and physical design methodologies. The role involves collaboration with RTL design, verification, foundry, and technology teams on microelectronics programs for secure and high-performance computing technologies.

The position requires U.S. citizenship and the ability to obtain and maintain a U.S. Government security clearance. Battelle describes a hybrid work arrangement, with 60% in-office and 40% remote work, and notes that many teams follow a flexible compressed schedule with every other Friday off, subject to team and position needs.

Requirements

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
• At least 3 years of physical design experience.
• Strong experience with physical design flows, including floor planning, placement, clock tree synthesis, routing, and optimization.
• Expertise in static timing analysis (STA) and timing-closure techniques.
• Knowledge of power analysis and power-optimization methodologies.
• Experience with signal integrity, IR-drop analysis, and EM/electromigration analysis.
• Proficiency in physical verification, including DRC, LVS, antenna, and ERC.
• Hands-on experience with industry-standard backend EDA tools, including Cadence Innovus.
• Scripting skills in TCL and Python for automation and flow development.
• Understanding of process technology nodes and design rules.
• Knowledge of clock domain crossing (CDC) and timing constraints.
• Familiarity with standard-cell libraries and design kits.
• Knowledge of version control, such as Git.
• Must be a U.S. citizen and able to obtain and maintain a U.S. Government security clearance.

Nice To Haves

• Experience with advanced technology nodes.
• Experience with ASIC subsystem integration, top-level assembly, IO ring development, manual layout, and coordination of physical implementation activities through signoff and tape-out.
• Knowledge of low-power design techniques, including power gating, multi-voltage, and retention.
• FinFET or Gate-All-Around (GAA) technology experience.
• High-speed design and advanced packaging knowledge.
• Multi-corner, multi-mode (MCMM) timing analysis experience.
• Experience with 3D IC or chiplet design.
• Knowledge of extraction tools and parasitic analysis.
• Knowledge of Design for Manufacturing (DFM) and Design for Yield (DFY) techniques.
• Understanding of thermal analysis and heat dissipation.
• Familiarity with advanced packaging, including 2.5D, 3D, and chiplet integration.
• Experience with assured microelectronics and hardware security principles, including cryptography, side-channel analysis, fault injection, radiation tolerance, and hardware CWEs.
• Active Secret or Top-Secret security clearance.

Responsibilities

• Execute physical design implementation from netlist to GDSII.
• Perform floor planning, power planning, and pin placement.
• Conduct placement optimization and clock tree synthesis (CTS).
• Perform detailed routing and optimize timing, power, and area.
• Achieve timing closure across corners and modes.
• Conduct power analysis and implement power reduction techniques.
• Perform signal integrity analysis and resolve signal-integrity and IR-drop violations.
• Execute physical verification checks, including DRC, LVS, antenna, and ERC.
• Generate timing constraints and perform static timing analysis.
• Collaborate with front-end design and verification teams.
• Work with foundry and technology teams on design-rule compliance.
• Create and maintain physical design documentation and reports.
• Develop and improve physical design methodologies and flows.
• Support signoff activities and tape-out preparations.
• Debug and resolve issues found during physical verification.

Benefits

• Flexible compressed work schedule, with most team members receiving every other Friday off.
• Hybrid work arrangement, with 60% in-office and 40% remote work, subject to team and position needs.
• Paid time off.
• Medical, dental, and vision coverage, with wellness incentives and optional supplemental benefits.
• Coverage and support for partners, gender-affirming care, and family formation.
• 401(k) retirement savings plan, with Battelle contributing 5% for most employees regardless of employee contributions and matching employee contributions.
• Tuition assistance for higher education.

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level