HW SOC/ASIC Physical Design Engineer, Senior/Staff (US Citizenship Required)

Qualcomm • San Diego, CA

2d • $121,800 - $182,600 • Onsite

About The Position

Qualcomm Technologies, Inc. is seeking a highly skilled and motivated Physical Design Engineer to support ASIC and SoC development. The role focuses on RTL-to-GDSII implementation, including floorplanning, placement, clock tree synthesis, routing, timing closure, physical verification, and power optimization. The engineer will develop robust, low-skew, power-efficient clock networks and help meet performance, power, and area goals. The position is full-time onsite in San Diego, California, five days per week. Applicants must be U.S. citizens eligible to receive a U.S. Government security clearance and must meet eligibility requirements for access to classified information; selected applicants will be subject to a government security investigation.

The position covers full-chip and block-level physical design, physical verification, static timing analysis, and low-power implementation. It involves developing and maintaining scripts and reference flows, validating ECOs and signoff results, resolving design and tool issues with internal teams and EDA vendors, coordinating with foundries on design rules and tapeout requirements, and supporting delivery of clean GDSII. The engineer applies ASIC knowledge to define, design, optimize, verify, validate, implement, and document IP, blocks, SoCs, or IC packages, working across teams to meet system requirements and customer needs.

The role works independently with minimal supervision. Its decisions may affect work beyond the immediate group, and the engineer may influence key organizational decisions. The work requires communication, planning, problem-solving, and prioritization across tasks that can involve multiple steps and execution paths.

Requirements

• Bachelor's degree in Science, Engineering, or a related field and 2 or more years of ASIC design, verification, validation, integration, or related work experience; or a Master's degree in Science, Engineering, or a related field and 1 or more years of such experience; or a PhD in Science, Engineering, or a related field.
• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
• At least 3 years of physical design experience, with a focus on clock tree design and implementation.
• Must be a U.S. citizen and eligible to receive a U.S. Government security clearance; selected applicants are subject to a government security investigation and must meet eligibility requirements for access to classified information.
• Strong understanding of digital timing concepts, clock domain crossing, and synchronous and asynchronous design.
• Proficiency with EDA tools for clock tree synthesis, static timing analysis, and physical verification, such as ICC2, Innovus, and PrimeTime.
• Experience with advanced process nodes such as 7nm, 5nm, or 3nm and FinFET technologies.
• Scripting skills in TCL, Python, and Perl for flow automation and data analysis.
• Familiarity with low-power design techniques, including clock gating and multi-voltage domains.
• Ability to work onsite in San Diego, California, five days per week.
• Ability to work independently with minimal supervision and communicate technical information verbally and in writing.
• Ability to plan, solve problems, and prioritize multi-step tasks.

Nice To Haves

• Experience with custom clock tree architectures such as H-tree, mesh, or spine-based topologies.
• Knowledge of EM/IR analysis, thermal-aware clocking, and reliability modeling.
• Exposure to high-speed interface clocking such as SerDes, DDR, or PCIe.
• Understanding of package-level clock planning and signal integrity.

Responsibilities

• Execute floorplanning, placement, clock tree synthesis, and routing using tools such as Innovus and ICC2.
• Drive timing closure across multiple modes and corners using static timing analysis tools such as PrimeTime.
• Collaborate with RTL designers to resolve timing, congestion, and DRC issues.
• Optimize designs for power, performance, and area (PPA).
• Conduct formal equivalence checks between RTL and netlists.
• Support physical verification, including DRC, LVS, and antenna checks.
• Work with backend teams on tapeout preparation and signoff.
• Execute full-chip and block-level physical verification, including DRC, LVS, ERC, antenna, and density checks.
• Customize and optimize physical verification flows for project needs and foundry requirements.
• Perform GDS-to-GDS comparisons to validate ECO changes, layout integrity, and tapeout readiness.
• Debug physical verification violations with layout, design, and CAD teams.
• Work with foundries to meet design rule manual and tapeout checklist requirements.
• Support signoff verification, including multi-corner/multi-mode analysis and ECO validation.
• Develop and maintain automation scripts for verification flows, reporting, and regression testing.
• Interface with EDA vendors to resolve tool issues and improve flow robustness.
• Participate in design reviews and provide feedback on layout quality, rule compliance, manufacturability, timing risks, and mitigation strategies.
• Ensure timely delivery of clean GDSII with full verification signoff.
• Perform full-chip and block-level static timing analysis using tools such as Synopsys PrimeTime and Cadence Tempus.
• Develop, validate, and maintain SDC timing constraints for multiple modes and corners.
• Collaborate with RTL, synthesis, and physical design teams on timing-aware design practices.
• Debug setup, hold, and transition violations across PVT corners.
• Drive timing closure through iterative optimization and ECO implementation.
• Customize and enhance timing analysis flows for accuracy, efficiency, and scalability.
• Analyze clock-tree timing, including skew, latency, and jitter impacts.
• Support signoff timing verification, including cross-domain timing and false- or multicycle-path handling.
• Define and implement low-power architecture using CLP methodology across RTL and physical design stages.
• Develop and maintain UPF/CPF power intent files and ensure alignment with design specifications.
• Integrate power-aware features such as power gating, retention, isolation, and level shifting with RTL, synthesis, and physical design teams.
• Perform power-aware static checks, simulation, and formal verification to validate power intent.
• Debug issues involving power-domain crossings, voltage islands, and power sequencing.
• Support signoff verification, including power-aware LVS/DRC, STA, and EM/IR analysis.
• Ensure compliance with foundry low-power guidelines and contribute to successful tapeout.
• Apply ASIC knowledge to define, model, design, optimize, verify, validate, implement, and document IP, block, or SoC development.
• Create architectures, circuit specifications, logic designs, and system simulations based on system-level requirements.
• Collaborate across software and hardware architecture teams to develop and execute implementation strategies that meet system requirements and customer needs.
• Evaluate process flows from high-level design through synthesis, place and route, timing, power, and verification, or the equivalent custom circuit design and layout flow.
• Use tools such as RTL-to-GDS flow tools and Virtuoso to enable architecture and design of blocks, SoCs, or IC packages.
• Write detailed technical documentation for EDA, IP, and ASIC projects.

Benefits

• Competitive annual discretionary bonus program.
• Opportunity for annual RSU grants; employees on sales-incentive plans are not eligible for the annual bonus.
• Competitive benefits package designed to support employees at work, at home, and at play.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior