MTS - HIG HBM - ARCHITECTURE

Micron Technology • Richardson, TX

2d

About The Position

Micron Technology, a world leader in memory and storage solutions, is seeking an HBM IO Design Architecture Engineer. This role is within the High-Performance Integrated Group (HIG), focused on developing and optimizing High Bandwidth Memory (HBM) solutions for AI and ML applications, aiming for the lowest power per bit solutions. The position involves HBM IO / TSV IO design and analysis, including electrical modeling, Signal Integrity (SI) and Power Integrity (PI) analysis, and design optimization throughout the HBM development cycle. The ideal candidate will have hands-on experience in design execution, simulation-to-silicon correlation, cross-functional methodology development, and will utilize AI-driven analysis and data-driven decision making to enhance quality improvement cycles.

Requirements

• Good IO circuit design background with familiarity of both, analog and digital design and simulation experience required
• Experience with circuit verification and optimization including layout verification and parasitic extractions of the circuits
• Good understanding on state-of-the-arts device characteristics and hands-on design experience
• Excellent problem-solving and analytical skills
• Strong documentation skills
• Strong communication skills with the ability to clearly convey sophisticated technical concepts to other design peers both verbally and written
• MS or PhD in EE
• 10+ years of relevant Engineering or Design Engineering experience on high-speed IO, PLL, Tx, Rx, Equalization, clock tree
• Familiarity with one or more high-speed interfaces such as HBM, DDR, UCIe, PCIe, or MIPI.

Nice To Haves

• Prior circuit debug experience through Product Engineering or equivalent preferred
• Knowledge of advanced packaging environments (CoWoS, HBM stack, D2D, etc)

Responsibilities

• High-speed IO design architecture for HBM products
• Define and standardize IO design quality process from architecture to silicon
• Define IO architecture, TSV IO performance targets, and design quality requirements for future HBM products.
• Develop IO and TSV modeling methodologies to support architecture tradeoff analysis, SI/PI evaluation, and design optimization.
• Drive simulation-to-silicon correlation and post-silicon learning feedback to improve design quality across HBM product generations.
• Leverage AI Assisted analytics to accelerate root cause identification from complex multi-variable silicon data

Benefits

• Choice of medical, dental and vision plans
• Benefit programs that help protect your income if you are unable to work due to illness or injury
• Paid family leave
• Robust paid time-off program
• Paid holidays

What This Job Offers

• Job Type: Full-time
• Career Level: Senior