FPGA Developer

AscendArc • Portland, OR

8h • Remote

About The Position

AscendArc is a venture-backed startup developing a new approach to satellite design and production to improve the bandwidth economics of GEO satellites and expand access to reliable, affordable connectivity. The FPGA Developer will develop communications technology for next-generation spacecraft, working across digital signal processing, software-defined radio, and spacecraft integration.

The role includes taking ownership of FPGA development and integrating existing modulation, demodulation, and packet-switching IP cores. The engineer will also develop custom DSP functionality and interfaces that enable spacecraft command, control, and communication with the radio. This is a collaborative, hands-on position involving technical direction, complex engineering problem-solving, and work from design through orbit.

Requirements

• B.S. or M.S. in Electrical Engineering, Computer Engineering, or equivalent experience.
• 8+ years of professional FPGA development in SystemVerilog and/or VHDL.
• Demonstrated experience integrating third-party or vendor IP cores into larger FPGA designs, including reading datasheets and user guides, configuring parameters, adapting interfaces, and verifying integrated behavior.
• Working understanding of packet-based routing and switching concepts, including arbitration, buffering, backpressure, and link-layer framing, sufficient to integrate and debug routing IP.
• Strong DSP fundamentals and hands-on experience implementing signal processing in fixed-point HDL, including filter design, sample-rate conversion, numerically controlled oscillators, and digital down/up-conversion.
• Practical experience with high-speed serial transceivers, such as GTH/GTY or equivalent Intel transceivers, including 8b/10b or 64b/66b encoding, comma alignment, and lane bonding.
• Proficiency with the full Vivado toolchain, including synthesis, implementation, timing analysis (STA), and constraint authoring (XDC/SDC).
• Strong verification skills, including self-checking testbenches, constrained-random stimulus, and coverage-driven methodology.
• Comfort with Git-based workflows and code review.

Nice To Haves

• RF and analog front-end experience, including working knowledge of RF chains, frequency planning, mixing, image rejection, and interaction between analog impairments and digital correction.
• Experience with high-speed converter interfaces such as JESD204B/C, including link bring-up and deterministic latency.
• Experience in space, defense, or other high-reliability environments, including radiation-tolerant design practices, TMR, scrubbing, and SEU mitigation.
• Familiarity with AXI/AXI-Stream interconnect and DMA architectures.
• Background in clock-domain crossing methodology and formal verification of CDC.
• Experience supporting hardware bring-up with lab instrumentation such as logic analyzers, spectrum analyzers, and signal generators.

Responsibilities

• Architect, write, and verify synthesizable RTL in SystemVerilog or VHDL for modern FPGAs.
• Integrate and configure modulation, demodulation, and packet-switching/routing IP cores, including parameterizing ports, configuring routing tables, connecting flow control and error/status interfaces, and validating end-to-end behavior.
• Implement DSP blocks in FPGA fabric, including FIR/CIC/polyphase filters, NCOs and mixers, decimation/interpolation chains, channelizers, and demodulation/synchronization logic.
• Develop simulation testbenches using UVM, cocotb, or similar; drive functional and code coverage; and own hardware bring-up.
• Take designs through synthesis, place-and-route, and timing closure; analyze utilization, congestion, and Fmax issues and resolve them at the RTL level.
• Integrate ADC/DAC front-ends and other mixed-signal interfaces, including clocking, calibration, and lane alignment.
• Collaborate with systems, firmware, and hardware engineers on interface definitions and hardware/software partitioning.
• Produce design documentation, interface control documents, and verification reports.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior