Formal Validation Engineer

Apple • Cupertino, CA

3d • $174,149 - $225,300 • Onsite

About The Position

Apple Inc. is hiring a Formal Validation Engineer in Cupertino, California, and various unanticipated locations throughout the USA. The role works on complete formal verification for one or multiple design blocks and IPs, including CPU, cellular and connectivity, audio and image processing, neural networks, memory/OMA controller, security, peripheral, interconnect, and power-management designs. The engineer works with Apple Silicon SoC and IP design engineers to develop formal microarchitecture specifications and comprehensive formal verification test plans; prove design properties, find design bugs, and work with design teams to improve microarchitecture; and create solutions for verifying complex design microarchitectures. The role also develops reusable, optimized formal models and verification code, and architects correct-by-construction design methodologies to improve formal verification efficiency and productivity. The position is 40 hours per week. Base pay is $174,149–$225,300 per year, depending on skills, qualifications, experience, and location. Apple also offers eligible employees discretionary stock awards and an employee stock purchase plan, along with medical and dental coverage, retirement benefits, discounted products, free services, and reimbursement for certain career-related educational expenses, including tuition. The role might also be eligible for discretionary bonuses or commission payments and relocation.

Requirements

• Bachelor’s degree or foreign equivalent in Computer Engineering, Electrical Engineering, Electronics Engineering, or a related field.
• Experience and/or education working with digital hardware design principles.
• Experience and/or education utilizing model-checking-based approaches to verify systems, such as hardware or protocols.
• Experience and/or education utilizing general formal methods principles.
• Experience and/or education communicating formal verification plans and results to dynamic validation and design partners.
• Experience and/or education analyzing computer architecture and SoCs.
• Experience and/or education with a hardware description language, including Verilog or VHDL, and using it to develop formal test benches.
• Experience and/or education using scripting languages including Python, Perl, or TCL in a hardware engineering and CAD context.

Responsibilities

• Perform complete formal verification for one or multiple design blocks and IPs.
• Work with Apple Silicon SoC and IP design engineers to develop formal microarchitecture specifications.
• Develop comprehensive formal verification test plans.
• Prove design properties and find design bugs.
• Work with design teams to improve microarchitecture.
• Develop creative solutions for verifying complex design microarchitectures.
• Develop reusable and optimized formal models and verification code.
• Architect correct-by-construction design methodologies to improve formal verification efficiency and productivity.

Benefits

• Comprehensive medical and dental coverage
• Retirement benefits
• Discounted products and free services
• Reimbursement for certain career-related educational expenses, including tuition
• Eligibility for discretionary restricted stock unit awards
• Opportunity to purchase Apple stock at a discount through the Employee Stock Purchase Plan
• Potential discretionary bonuses or commission payments
• Potential relocation assistance

What This Job Offers

• Job Type: Full-time