Formal Validation Engineer

Apple•Cupertino, CA

About The Position

Apple Inc. is hiring a Formal Validation Engineer to work on complete formal verification for one or more design blocks and IPs, including CPU, cellular and connectivity, audio and image processing, neural networks, memory/DMA controllers, security, peripheral IP, interconnects, and power management subsystems. The role partners with Apple Silicon SOC and IP design engineers to develop formal micro-architecture specifications and comprehensive verification test plans. The engineer will improve micro-architecture by proving properties, finding bugs, and applying digital logic design and computer architecture knowledge. The position also develops creative approaches to verifying complex design micro-architectures, implements reusable and optimized formal models and verification code, and architects correct-by-construction design methodologies to improve formal verification efficiency and productivity. The role is based in Cupertino, California, and various unanticipated locations throughout the USA, and is 40 hours per week.

Requirements

  • Master’s degree or foreign equivalent in Electrical Engineering, Electronics Engineering, or a related field.
  • At least 2 years of experience in the job offered or a related occupation.
  • At least 2 years of experience using design verification techniques, tools, and methodologies to verify and improve chip design and architecture.
  • At least 2 years of experience designing and implementing verification environments using Verilog and SystemVerilog.
  • At least 2 years of experience architecting correct-by-construction design methodologies for improved verification efficiency.
  • At least 2 years of experience using scripting languages to develop and maintain verification infrastructure.
  • At least 2 years of experience using programming languages such as C and C++ to verify complex data path designs.
  • At least 2 years of design verification experience running regressions, determining root causes of failing designs, tracking bugs, and analyzing coverage.
  • At least 2 years of experience using SoC design and verification knowledge to drive and maintain deliverables and support cross-functional engineering.
  • At least 2 years of experience leveraging design knowledge to drive design teams and improve SoC architecture.
  • At least 2 years of experience using RTL debugging and digital system design to achieve design performance and functional goals.

Responsibilities

  • Perform complete formal verification for one or more design blocks and IPs, such as CPU, cellular and connectivity, audio and image processing, neural networks, memory/DMA controllers, security, peripheral IP, interconnects, and power management subsystems.
  • Collaborate with Apple Silicon SOC and IP design engineers to develop formal micro-architecture specifications.
  • Develop comprehensive verification test plans.
  • Improve micro-architecture by proving properties, finding bugs, and performing digital logic design and computer architecture work.
  • Develop creative solutions for verifying complex design micro-architectures.
  • Develop and implement reusable, optimized formal models and verification code.
  • Architect correct-by-construction design methodologies to improve formal verification efficiency and productivity.
  • Run regressions, investigate failing designs, track bugs, and analyze coverage.
  • Support cross-functional engineering and drive and maintain design and verification deliverables.

Benefits

  • Opportunity to participate in discretionary employee stock programs, including restricted stock unit awards.
  • Employee Stock Purchase Plan with the option to purchase Apple stock at a discount.
  • Comprehensive medical and dental coverage.
  • Retirement benefits.
  • Discounted products and free services.
  • Reimbursement for certain education expenses, including tuition, for formal education related to career advancement at Apple.
  • Potential eligibility for discretionary bonuses or commission payments.
  • Potential relocation assistance.
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