Apple Inc. is hiring a Formal Validation Engineer to work on complete formal verification for one or more design blocks and IPs, including CPU, cellular and connectivity, audio and image processing, neural networks, memory/DMA controllers, security, peripheral IP, interconnects, and power management subsystems. The role partners with Apple Silicon SOC and IP design engineers to develop formal micro-architecture specifications and comprehensive verification test plans. The engineer will improve micro-architecture by proving properties, finding bugs, and applying digital logic design and computer architecture knowledge. The position also develops creative approaches to verifying complex design micro-architectures, implements reusable and optimized formal models and verification code, and architects correct-by-construction design methodologies to improve formal verification efficiency and productivity. The role is based in Cupertino, California, and various unanticipated locations throughout the USA, and is 40 hours per week.
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Job Type
Full-time
Career Level
Mid Level