Formal Validation Engineer

Apple • Cupertino, CA

3d • $207,673 - $277,600

About The Position

Apple Inc. is hiring a Formal Validation Engineer to work on complete formal verification for one or more design blocks and IPs, including CPU, cellular and connectivity, audio and image processing, neural networks, memory/DMA controllers, security, peripheral IP, interconnects, and power-management subsystems. The role collaborates with Apple Silicon SoC and IP design engineers to develop formal micro-architecture specifications and comprehensive verification test plans. It also supports micro-architecture improvement through property proving, bug finding, and work in digital logic design and computer architecture.

The engineer develops creative approaches to verifying complex design micro-architectures, builds reusable and optimized formal models and verification code, and architects correct-by-construction design methodologies to improve verification efficiency and productivity. The schedule is 40 hours per week. The stated base-pay range is $207,673–$277,600 per year, with pay dependent on skills, qualifications, experience, and location.

Requirements

• Master’s degree or foreign equivalent in Electrical Engineering, Electronics Engineering, or a related field.
• At least 2 years of experience in the job offered or a related occupation.
• At least 2 years of experience using design verification techniques, tools, and methodologies to verify and improve chip design and architecture.
• At least 2 years of experience designing and implementing a verification environment using Verilog and System Verilog.
• At least 2 years of experience architecting correct-by-construction design methodologies for improved verification efficiency.
• At least 2 years of experience using scripting languages to develop and maintain verification infrastructure.
• At least 2 years of experience using programming languages such as C and C++ to verify complex data-path designs.
• At least 2 years of experience running regressions, including root-causing failing designs, bug tracking, and analyzing coverage.
• At least 2 years of experience using SoC design and verification knowledge to drive and maintain deliverables and support cross-functional engineering.
• At least 2 years of experience using design knowledge to drive design teams and improve SoC architecture.
• At least 2 years of experience using RTL debugging and digital system design to achieve design performance and functional goals.

Responsibilities

• Perform complete formal verification for one or more design blocks and IPs.
• Work with Apple Silicon SoC and IP design engineers to develop formal micro-architecture specifications.
• Develop comprehensive verification test plans.
• Help improve micro-architecture by proving properties, finding bugs, and performing digital logic design and computer architecture work.
• Develop creative solutions for verifying complex design micro-architectures.
• Develop and implement reusable, optimized formal models and verification code.
• Architect correct-by-construction design methodologies to improve formal verification efficiency and productivity.

Benefits

• Opportunity to participate in discretionary employee stock programs, including discretionary restricted stock unit awards and discounted Apple stock through the Employee Stock Purchase Plan.
• Comprehensive medical and dental coverage.
• Retirement benefits.
• Discounted products and free services.
• Reimbursement for certain educational expenses, including tuition, for formal education related to career advancement at Apple.
• May be eligible for discretionary bonuses or commission payments.
• May be eligible for relocation assistance.

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level