FE Engineer

Apple•Cupertino, CA

6d•$150,400 - $225,300•Onsite

About The Position

Work with leads and architecture teams to define the design microarchitecture. Develop RTL design of one or more blocks following established design guidelines based on microarchitecture spec. Own all aspects of RTL development design. Work and collaborate with other designers in the group to deliver results. Integrate common/shared IP blocks and optimize memories/hard macros required for the block. Complete front-end synthesis/STA to ensure timing for the block is met. Optimize power/performance. Collaborate with multi-disciplinary groups to make sure designs are delivered on time and of the highest quality by incorporating proper checks at every stage of the design process. 40 hours/week.

Requirements

Master’s degree or foreign equivalent in Electrical Engineering or related field and 2 years of experience in the job offered or related occupation.
2 years of experience utilizing System Verilog or Verilog to write RTL for CPU-based SoCs.
2 years of experience utilizing CDC tools/techniques and knowledge of multiple clock domains to fix the issues.
Experience in RTL Design with AMBA protocols, such as AHB.
Experience utilizing industry standard simulation tools to verify and debug functional behavior of an SoC or IP block-level design.
Experience configuring and integrating digital and analog IPs into an SoC/sub-system.
Experience analyzing timing and resolving timing violations at digital-analog interfaces.
Experience utilizing LINT tools to ensure RTL coding meets industry guidelines.
Experience validating and debugging system silicon functionality during chip bring-up.

Responsibilities

Define the design microarchitecture.
Develop RTL design of one or more blocks following established design guidelines based on microarchitecture spec.
Own all aspects of RTL development design.
Work and collaborate with other designers in the group to deliver results.
Integrate common/shared IP blocks and optimize memories/hard macros required for the block.
Complete front-end synthesis/STA to ensure timing for the block is met.
Optimize power/performance.
Collaborate with multi-disciplinary groups to make sure designs are delivered on time and of the highest quality by incorporating proper checks at every stage of the design process.