FE Engineer

Apple•Cupertino, CA

5d•Onsite

About The Position

Imagine what you can do here. Apple is a place where extraordinary people gather to do their lives best work. Together we create products and experiences people once couldn't have imagined, and now, can't imagine living without. It's the diversity of those people and their ideas that inspires the innovation that runs through everything we do. APPLE INC has the following available in Cupertino, California and various unanticipated locations throughout the USA.

Requirements

Utilizing System Verilog or Verilog to write RTL for CPU-based SoCs.
Utilizing CDC tools/techniques and knowledge of multiple clock domains to fix the issues.
Experience in RTL Design with AMBA protocols, such as AHB.
Utilizing industry standard simulation tools to verify and debug functional behavior of an SoC or IP block-level design.
Configuring and integrating digital and analog IPs into an SoC/sub-system.
Analyzing timing and resolving timing violations at digital-analog interfaces.
Utilizing LINT tools to ensure RTL coding meets industry guidelines.
Validating and debugging system silicon functionality during chip bring-up.

Responsibilities

Work with leads and architecture teams to define the design microarchitecture.
Develop RTL design of one or more blocks following established design guidelines based on microarchitecture spec.
Own all aspects of RTL development design.
Work and collaborate with other designers in the group to deliver results.
Integrate common/shared IP blocks and optimize memories/hard macros required for the block.
Complete front-end synthesis/STA to ensure timing for the block is met.
Optimize power/performance.
Collaborate with multi-disciplinary groups to make sure designs are delivered on time and of the highest quality by incorporating proper checks at every stage of the design process.