FE Engineer

Apple • Austin, TX

4d • Onsite

About The Position

Imagine what you can do here. Apple is a place where extraordinary people gather to do their lives best work. Together we create products and experiences people once couldn't have imagined, and now, can't imagine living without. It's the diversity of those people and their ideas that inspires the innovation that runs through everything we do. APPLE INC has the following available in Austin, Texas. Integrate Internal and external IP (Intellectual Property), designing system bus and control bus logic for connectivity of IP blocks to the main SOC infrastructure. Own the Integration Spec for the design project. Integrate and optimize any memories and hard macros required for the block. Run synthesis, netlist generation, and timing closure for the block. Work closely with Chip Architecture, Design verification, Physical Design, DFT (Design for Test), and power teams to achieve first tape out success on designs. Develop and maintain methodology/flows/checks for owned designs. Work with multi-disciplinary groups to make sure designs are delivered on time and with highest quality by incorporating proper checks at every stage of the design process.

Requirements

• Using System Verilog or Verilog to write RTL for Integration components
• Utilizing multiple clock domains, reset domains and applying techniques to fix the issues
• Utilizing low power design concepts like clock gating, power gating and DVFS to meet low power design targets
• Utilizing Synthesis tools from Synopsys or Cadence to use timing constraints to synthesize designs
• Integrate RTL components into sub-systems interfacing with memories
• Utilizing Design-for-test concepts to support scan insertion for overall testability
• Utilizing CAD tools to ensure quality of design

Responsibilities

• Integrate Internal and external IP (Intellectual Property), designing system bus and control bus logic for connectivity of IP blocks to the main SOC infrastructure.
• Own the Integration Spec for the design project.
• Integrate and optimize any memories and hard macros required for the block.
• Run synthesis, netlist generation, and timing closure for the block.
• Work closely with Chip Architecture, Design verification, Physical Design, DFT (Design for Test), and power teams to achieve first tape out success on designs.
• Develop and maintain methodology/flows/checks for owned designs.
• Work with multi-disciplinary groups to make sure designs are delivered on time and with highest quality by incorporating proper checks at every stage of the design process.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior