Director, Physical Design & CAD Methodology (ASIC/SoC)

Cisco•San Jose, CA

2d•$230,100 - $374,100

About The Position

The Common Hardware Group (CHG) creates innovative hardware platforms central to the AI era, powering Cisco’s core Switching, Routing, and Wireless products for organizations globally. Our innovations in silicon, optics, and hardware platforms—like Silicon One—are shaping the technology industry. We're a global team of creative experts, bringing our unique backgrounds and bold ideas to push boundaries and help each other grow. Because full product development—from design to qualification to production—is within our team, we’re able to think differently, experiment more, and work quickly. Join us to power the future of the digital world.

Requirements

Master’s or Ph.D. degree in Electrical Engineering, Computer Engineering, or a highly related technical field with 10+ years of experience in ASIC/SoC physical design and CAD methodology.
5+ years of experience in a formal leadership or people management role
Experience navigating the complexities of advanced process geometries (7nm, 5nm, 3nm and 2nm)
Experience with full RTL-to-GDSII design flows
Experience with physical verification (DRC, LVS, ERC), Static Timing Analysis (STA), sign-off processes, and power integrity (IR drop and electromigration)

Nice To Haves

Proficiency in EDA tool suites (e.g., Innovus, Fusion Compiler, PrimeTime, Calibre)

Responsibilities

Define the global physical design methodology strategy across all phases: synthesis, floor planning, placement, clock tree synthesis (CTS), routing, timing closure, and physical verification.
Architect and deploy advanced CAD flows to support complex, high-performance System-on-Chip (SoC) and Application-Specific Integrated Circuit (ASIC) designs.
Drive innovation in hierarchical design, multi-die/chiplet integration, and 2.5D/3D IC Design methodologies.
Manage, mentor, and grow a high-performing team of CAD and physical design methodology engineers.
Allocate engineering resources efficiently to support concurrent, multi-project execution timelines.
Develop a culture of continuous learning, automation, and technical excellence.
Serve as the primary technical liaison with major EDA vendors (e.g., Synopsys, Cadence, Siemens).
Evaluate, benchmark, and select state-of-the-art EDA tools to improve engineering productivity and design quality.
Negotiate tool licensing requirements, influence vendor product roadmaps, and manage the CAD budget.
Drive the creation of robust scripting infrastructure (using Tcl, Python, Perl) to automate repetitive tasks and ensure flow consistency.
Explore and integrate AI/ML-driven EDA features to optimize PPA and shorten turnaround times.
Partner closely with RTL Design, DFT (Design for Test), Architecture, and Physical Implementation teams to ensure seamless handoffs and tool interoperability.
Collaborate with external foundries to integrate Process Design Kits (PDKs) and resolve complex deep sub-micron physical effects (e.g., electromigration, IR drop, thermal management).

Benefits

medical, dental and vision insurance
a 401(k) plan with a Cisco matching contribution
paid parental leave
short and long-term disability coverage
basic life insurance
grants of Cisco restricted stock units
10 paid holidays per full calendar year
1 floating holiday for non-exempt employees
1 paid day off for employee’s birthday
paid year-end holiday shutdown
4 paid days off for personal wellness
16 days of paid vacation time per full calendar year (non-exempt employees)
flexible vacation time off program (exempt employees)
80 hours of sick time off provided on hire date and each January 1st thereafter
up to 80 hours of unused sick time carried forward from one calendar year to the next
Additional paid time away may be requested to deal with critical or emergency issues for family members
Optional 10 paid days per full calendar year to volunteer
annual bonuses (for non-sales roles)
performance-based incentive pay (for sales roles)