Sr. Staff ASIC Design Methodology Engineer, AI HW

Tenstorrent Unlisted/Referral Jobs•Toronto, ON

6d•$100,000 - $500,000•Hybrid

About The Position

Tenstorrent is seeking a Sr. Staff ASIC Design Methodology Engineer for our AI Hardware Tensix team. In this role, you will advance our design infrastructure and flows across RTL development, verification, and physical implementation specifically for our core AI compute engines. This role is ideal for senior engineers who thrive on improving design quality, enabling scalability, and automating methodologies that accelerate the silicon success of our next-generation Tensix cores. This role is hybrid, based out of Toronto, ON. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Requirements

A strong advocate for design quality and productivity, with deep expertise in ASIC design flows and a track record of leading methodology improvements.
Skilled in RTL design and an expert in static and dynamic analysis tools tailored for high-performance AI hardware.
A technical leader comfortable automating design checks and improving methodology for scalability and reuse across complex Tensix core configurations.
A collaborative engineer who partners effectively across RTL, verification, and backend teams to ensure seamless execution.

Nice To Haves

How large-scale AI SoCs are architected, integrated, and brought to silicon using Tenstorrent's unique Tensix technology.
How methodology choices directly impact design performance, power, and verification closure in the context of massive AI compute arrays.
How to build and scale ASIC design flows supporting cutting-edge compute architectures and RISC-V integration.
How to integrate cross-functional workflows across design, DFT, DV, physical, and firmware teams to deliver world-class AI hardware.

Responsibilities

Develop and maintain ASIC design methodologies and infrastructure for RTL development and integration within the Tensix team.
Own and evolve static code analysis (Lint, CDC, RDC, DFT) and RTL-netlist logic equivalency design methodologies to ensure high-quality AI hardware delivery.
Develop synthesis timing constraints (SDC) and low power design specifications (UPF) to optimize the power-efficiency of our AI compute engines.
Support RTL-to-GDS flow enablement, ensuring clean handoffs and sign-off readiness for our cutting-edge AI SoCs.
Collaborate with EDA vendors and internal tool owners to optimize performance, quality, and runtime for Tensix-specific workloads.