Digital Layout Design Engineer

Apple•San Diego, CA

About The Position

As part of Apple’s Digital Design Engineering group and custom layout team, the Digital Layout Design Engineer works on state-of-the-art ASICs and the latest technology nodes to create custom digital macros and libraries. The role is part of the microprocessor group’s layout team and focuses on delivering PDV-clean layouts for digital circuits in deep SubMicron CMOS technologies. The engineer collaborates with circuit designers and teams in integration, CAD, circuit, and technology engineering to develop layouts and resolve design tradeoffs.

Requirements

  • A minimum of a bachelor's degree in a related field.
  • Experience in custom layout design of deep SubMicron CMOS circuits.
  • High proficiency in layout floorplanning, standard cell planning, and hierarchical layout assembly.
  • Good understanding of RC delay, electromigration, self heating, and cross capacitance issues.
  • Ability to recognize failure-prone layout structures and work with designers to determine effective approaches.
  • Excellent communication skills and ability to work with multifunctional teams.
  • Strong ability to interpret CALIBRE DRC, ERC, and LVS reports.
  • Knowledge of MENTOR GRAPHICS or CADENCE layout tools.

Nice To Haves

  • Scripting skills in CSH, PERL, or SKILL.
  • Experience in layout automation.
  • Experience in memory compiler development.
  • Experience designing low-noise, low-power datapaths or memory layout structures.

Responsibilities

  • Design complex custom layouts for digital circuits in deep SubMicron CMOS technologies.
  • Review and analyze floorplans and complex circuits with circuit designers.
  • Run the complete set of available layout design verification tools on completed megacells.
  • Work with the circuit design team to plan and schedule work and negotiate layout tradeoffs.
  • Interpret LVS, DRC, and ERC reports to identify an efficient path to completing layouts.
  • Meet or exceed engineering specifications and expectations.
  • Use advanced CAD tools and mask design knowledge to make layout corrections and create robust physical representations of circuits.
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