Digital Design Verification Engineer

Broadcom • San Jose, CA

4d • $101,000 - $162,000

About The Position

The ideal candidate has a proven track record of working on setting up testbenches for Design Verification using UVM on large designs. Responsibilities include operating with a high degree of autonomy, taking designs from initial specification through to timing closure and physical design hand-off. This role also involves collaborating cross-functionally with Architecture, Verification, and Physical Design teams to mitigate risks and ensure project milestones are met on schedule.

Requirements

• BSEE required
• 5+ years of industry experience with a focus on SoC integration, UVM test bench setup and design debug.
• High proficiency in UVM

Nice To Haves

• MSEE/PHD preferred

Responsibilities

• Operate with a high degree of autonomy, taking designs from initial specification through to timing closure and physical design hand-off
• Collaborate cross-functionally with Architecture, Verification, and Physical Design teams to mitigate risks and ensure project milestones are met on schedule

Benefits

• Discretionary annual bonus
• Competitive new hire equity grant
• Annual equity awards
• Medical plans
• Dental plans
• Vision plans
• 401(K) participation including company matching
• Employee Stock Purchase Program (ESPP)
• Employee Assistance Program (EAP)
• Company paid holidays
• Paid sick leave
• Vacation time
• Paid Family Leave
• Other leaves of absence

What This Job Offers

• Job Type: Full-time
• Career Level: Senior