Digital Design Verification Engineer

Broadcom • San Jose, CA

2d • $101,000 - $162,000

About The Position

The ideal candidate has a proven track record of working on setting up testbenches for Design Verification using UVM on large designs. Responsibilities include: Operate with a high degree of autonomy, taking designs from initial specification through to timing closure and physical design hand-off Collaborate cross-functionally with Architecture, Verification, and Physical Design teams to mitigate risks and ensure project milestones are met on schedule.

Requirements

• High proficiency in UVM
• BSEE required
• 5+ years of industry experience with a focus on SoC integration, UVM test bench setup and design debug.

Nice To Haves

• MSEE/PHD preferred

Responsibilities

• Operate with a high degree of autonomy, taking designs from initial specification through to timing closure and physical design hand-off
• Collaborate cross-functionally with Architecture, Verification, and Physical Design teams to mitigate risks and ensure project milestones are met on schedule

Benefits

• discretionary annual bonus
• competitive new hire equity grant
• annual equity awards
• Medical, dental and vision plans
• 401(K) participation including company matching
• Employee Stock Purchase Program (ESPP)
• Employee Assistance Program (EAP)
• company paid holidays
• paid sick leave
• vacation time
• Paid Family Leave
• other leaves of absence

What This Job Offers

• Job Type: Full-time
• Career Level: Senior