Design Engineer II

Silicon Labs•Austin, TX

4d•$101,500 - $188,500•Hybrid

About The Position

As a Digital Design Engineer II at Silicon Labs, you will develop highly integrated, low-power System-on-Chip (SoC) devices for the IoT wireless market. The role covers SoC architecture, RTL design, IP integration, synthesis and analysis, verification, and silicon validation throughout the development lifecycle. You will work with digital and mixed-signal subsystems, processors, power and clock domains, and backend teams to optimize designs for customer scenarios and for power, performance, and area. You will also support cross-functional teams during validation and bring-up.

Requirements

Master’s degree in Electrical Engineering.
3–5 years of professional experience in digital CMOS IC design.
Verilog RTL design experience, including taking designs through the silicon development lifecycle to production.
Knowledge of embedded processor systems and C coding.
Experience with logic simulators for RTL and gate-level simulation, design and waveform browsers, and power analysis tools.
Experience with logic synthesis and timing constraints.
Experience working with analog and mixed-signal designs to support subsystem integration and verification in SoCs.
Experience with scripting and automation.
Experience with revision control and configuration management systems, such as Perforce, Git, or Methodics.
Excellent written and verbal communication skills.
Demonstrated ability to produce high output in a self-driven manner.
Experience with AI-powered tools and technologies used to enhance productivity, analysis, and decision-making.

Responsibilities

Develop complex SoC and chip architectures with multiple processors, digital and mixed-signal subsystems, and multiple power and clock domains, optimizing power for specific customer scenarios.
Design RTL modules using SystemVerilog HDL and adhere to quality standards.
Prepare and conduct architecture, design, and verification reviews with technical staff throughout the project lifecycle.
Configure and integrate digital and mixed-signal IPs at the SoC level, including processors, memories and controllers, busses, power and clocking systems, security systems, machine learning, radio systems, analog IP, and pads.
Perform logic synthesis and full-chip timing and power analysis to optimize designs for key customer scenarios.
Work with the backend team to optimize designs for power, performance, and area.
Perform pre-silicon verification using a combination of block- and chip-level test benches.
Validate and bring up designs on silicon, supporting cross-functional teams.

Benefits

Medical plans, including a choice of PPO or Consumer Driven Health Plan with HSA.
Dental and vision plans.
401(k) plan with match and Roth plan option.
Equity rewards (RSUs).
Life/AD&D and disability coverage.
Flexible spending accounts.
Adoption assistance.
Back-up childcare.
Commuter benefits.
Legal benefits.
Pet insurance.
Flexible PTO schedule.
Three paid volunteer days per year.
Charitable contribution match.
Tuition reimbursement.
Free downtown parking.
Onsite gym.
Monthly wellness offerings.
Free snacks.