Digital CAD DFT Methodology, Sr Architect-19503

Synopsys•Sunnyvale, CA

14d•$239,200 - $358,800•Onsite

About The Position

Synopsys is hiring a senior DFT architect to develop and deploy test solutions for complex ASIC and SoC designs. The role provides technical leadership across customer and internal programs, advancing DFT methodologies and helping teams deliver scalable, production-ready test solutions. The position is in the Digital Methodology Center of Excellence and works closely with R&D, product engineering, customer success, and strategic accounts to shape DFT methodologies and support adoption of advanced test solutions. The position may be located in California, Texas, or Oregon; the posting lists Sunnyvale, California, and indicates that it is not remote eligible. The role focuses on Synopsys TestMAX DFT, ATPG, diagnosis, and silicon lifecycle solutions, as well as advanced DFT architectures and standards-based test access and instrumentation. It also contributes to methodology improvements, customer engagements, automation, and engineering mentorship. The position may be eligible for an annual bonus, equity, and other discretionary bonuses, in addition to base salary. The stated U.S. base salary range is $239,200–$358,800; actual compensation depends on job-related factors including location, skills, experience, and education.

Requirements

BS or MS in Electrical Engineering, Computer Engineering, or a related field.
18+ years of experience in the semiconductor or EDA industry, including deep experience in DFT, ATPG, and manufacturing test methodologies.
Demonstrated expertise architecting and implementing DFT solutions for large-scale ASIC and SoC designs.
Hands-on experience with Synopsys TestMAX DFT and TestMAX ATPG solutions.
Strong understanding of scan insertion, scan compression, hierarchical DFT, ATPG, diagnosis, coverage optimization, and test cost reduction techniques.
Expertise with IEEE 1149.1, IEEE 1149.6, IEEE 1687, and IEEE 1500 standards.
Experience developing and deploying JTAG/TAP architectures, boundary scan networks, IJTAG instrumentation networks, and embedded instrument access solutions.
Expertise integrating DFT IP, including embedded compression, OCC, LBIST, TAP controllers, JTAG/IJTAG infrastructure, TDR networks, and IEEE 1500 wrappers.
Strong understanding of RTL-to-GDSII implementation flows and the interaction between DFT, synthesis, physical design, timing closure, and signoff.
Proficiency in Tcl, Python, Perl, Shell, or similar scripting languages for methodology development and automation.
Ability to provide strategic technical leadership, influence engineering direction, and support customers, partners, and internal stakeholders.
Exceptional communication skills, including presenting complex technical concepts to diverse audiences.
Collaborative, results-driven approach and a passion for solving challenging DFT problems.

Responsibilities

Drive advanced DFT methodologies for complex ASIC and SoC programs across customer and internal engagements.
Serve as a senior technical expert for Synopsys TestMAX DFT, ATPG, diagnosis, and silicon lifecycle solutions.
Lead deployment of advanced DFT architectures, including scan compression, hierarchical DFT, boundary scan, IEEE 1500 wrapper solutions, IJTAG infrastructures, and embedded test technologies.
Architect scalable test access and instrumentation networks using IEEE 1149.1, IEEE 1149.6, IEEE 1687, and IEEE 1500 standards.
Develop best practices for DFT insertion, ATPG generation, pattern validation, diagnosis, and coverage optimization.
Drive reusable methodologies, automation, and signoff criteria to improve deployment quality and engineering efficiency.
Partner with R&D teams to influence product capabilities and methodology improvements.
Support strategic customer engagements, methodology reviews, and complex technical escalations.
Mentor engineers and strengthen DFT expertise across the organization.