DFT Intern - Fall 2026
Etched•San Jose, CA
•Onsite
About The Position
As a DFT Intern at Etched, you will help review and refine DFT flow automation to support chip-level regression on Caelius. You will work across frontend and backend design teams, contribute to DFT verification (including MBIST, Scan, BSCAN, and SSN simulations), and develop flows for various ATPG fault models. You do not necessarily need prior DFT experience; just the ability to learn quickly in a fast-paced, high-autonomy environment.
Requirements
- Progress towards a Bachelor's, Master's, or PhD degree in electrical engineering, computer engineering, or a related field.
- Familiarity with a hardware description language (Verilog or SystemVerilog)
- Exposure to ASIC or SoC design concepts
- Familiarity with digital logic design fundamentals
- Familiarity with standard ASIC design flow steps (synthesis, STA, DFT)
- Familiarity with scripting in Python, Tcl, or another language
- Able to learn quickly about transformers and other aspects of modern artificial intelligence
Nice To Haves
- Knowledge of DFT concepts such as MBIST, scan insertion, and scan compression
- Experience with Tessent or similar DFT tooling
- Familiarity with ATPG fault models (SAF, TDF, BDF, IDDQ, PDF)
- Exposure to DFT flow automation or regression infrastructure
- Familiarity with clocking and reset schemes
Responsibilities
- Review and refine DFT flow automation to support chip-level regression on Caelius.
- Work across frontend and backend design teams.
- Contribute to DFT verification (including MBIST, Scan, BSCAN, and SSN simulations).
- Develop flows for various ATPG fault models.
Benefits
- 12-week paid internship
- Generous housing support for those relocating
- Daily lunch and dinner in our office
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What This Job Offers
Career Level
Intern
Education Level
No Education Listed
