Design Verification Manager

Hewlett Packard Enterprise • Sunnyvale, CA

1d • Onsite

About The Position

We are seeking a visionary and technically rigorous Design Verification Manager to lead our world-class silicon verification team. In this pivotal leadership role, you will architect, guide, and execute advanced verification strategies for high-performance, next-generation semiconductor products. As a manager, you will bridge the gap between high-level architectural complexity and flawlessly executed silicon. You will be responsible for leading an elite engineering group, driving the adoption of cutting-edge methodology, and ensuring zero-bug tape-outs. If you thrive on solving complex microarchitectural puzzles, scaling high-performing teams, and pushing the boundaries of pre-silicon validation quality, this role offers an unparalleled opportunity to make an industry-wide impact.

Requirements

• Bachelor’s degree in Electrical Engineering, Computer Science, Computer Engineering, or a closely related technical field.
• 10 + years of deep, hands-on industry experience in pre-silicon ASIC/SoC Design Verification.
• 5 + years of dedicated engineering management or formal team leadership experience directly managing engineering headcount, performance reviews, and project delivery schedules.
• Proven mastery building scalable UVM-compliant testbenches from scratch.
• Deep, expert-level fluency in SystemVerilog and Universal Verification Methodology (UVM) architecture.
• Proven track record of leveraging formal methods to definitively mathematically prove block-level assertions and catch deep corner-case bugs.
• Strategic experience utilizing emulation platforms (e.g., Palladium, Zebu, Veloce) to shift-left software integration and accelerate massive system-level test suites.

Nice To Haves

• Master's degree or Ph.D. in Electrical Engineering or Computer Science.
• Exposure to, or hands-on experience implementing, Artificial Intelligence and Machine Learning techniques within verification pipelines (e.g., using AI/ML for smart stimulus generation, coverage convergence acceleration, automated bug triage, or regression optimization).
• Experience with multi-protocol high-speed interfaces (e.g., PCIe Gen6/7, CXL, HBM3, NVLink ).
• Demonstrated capability to manage globally distributed engineering teams.

Responsibilities

• Manage, inspire, and grow a team of high-performing design verification engineers.
• Foster a culture of technical excellence, continuous learning, and collaborative accountability.
• Allocating resources effectively across multiple parallel chip/block schedules.
• Define global verification strategies, infrastructure, and execution plans for complex SoC and IP blocks.
• Own the testbench architecture from initial specifications down to structural sign-off.
• Drive standard-setting execution using industry-best paradigms, ranging from advanced functional metric tracking to pioneering automated flows.
• Lead the team across block, sub-system, and full-chip verification environments.
• Align closely with Architecture, RTL Design, Physical Design, and Post-Silicon validation teams to identify coverage gaps, debug system-level failures, and ensure timely tape-out milestones.

Benefits

• Health & Wellbeing: We strive to provide our team members and their loved ones with a comprehensive suite of benefits that supports their physical, financial and emotional wellbeing.
• Personal & Professional Development: We also invest in your career because the better you are, the better we all are. We have specific programs catered to helping you reach any career goals you have — whether you want to become a knowledge expert in your field or apply your skills to another division.
• Unconditional Inclusion: We are unconditionally inclusive in the way we work and celebrate individual uniqueness. We know varied backgrounds are valued and succeed here. We have the flexibility to manage our work and personal needs. We make bold moves, together, and are a force for good.

What This Job Offers

• Job Type: Full-time
• Career Level: Manager