Design Verification Engineer

Apple•Waltham, MA

17d•$123,850 - $175,200•Onsite

About The Position

Apple Inc. is seeking a Design Verification Engineer in Waltham, Massachusetts. This role involves using both functional and formal verification methods to ensure bug-free delivery of features. The engineer will develop detailed test and coverage plans based on microarchitecture, create a verification methodology suitable for the IP, and ensure a scalable and portable environment. Responsibilities include developing a verification environment with components like stimulus, checkers, assertions, trackers, and coverage. The role also entails developing and executing verification plans for all features, including design and DV environment bring-up, enabling regressions for features under their care, and debugging test failures. The engineer will develop block, IP, and SoC level test-benches, track and report DV progress using metrics like bugs and coverage, and utilize EDA tools such as Cadence Xcelium for simulation, VManager for test plan development, Virtuoso for schematic viewing, Jasper Gold for formal verification, and Verdi for waveform viewing and debugging. The position is for 40 hours/week.

Requirements

Master’s degree or foreign equivalent in Computer Engineering or related field.
Developing detailed test plans from design specifications
Using SystemVerilog to verify high performance VLSI designs
Using Universal Verification Methodology (UVM) to develop testbenches, tests, sequences, scoreboards, assertions, and coverage objects
Setting up and executing regression suites
Root-cause debugging of regression failures
Analyzing functional and code coverage reports and closing coverage gaps
Using Python, Perl, or Tcl to automate tasks
Utilization of formal verification tools

Responsibilities

Use both functional and formal verification to ensure bug-free delivery of features.
Develop detailed test and coverage plans based on the microarchitecture.
Develop verification methodology suitable for the IP, ensuring a scalable and portable environment.
Develop a verification environment, including all the respective components such as stimulus, checkers, assertions, trackers, and coverage.
Develop verification plans for all features.
Execute verification plans, including design bring-up, DV environment bring- up, regression enabling all features under my care, and debug of the test failures.
Develop block, IP and SoC level test-benches
Track and report DV progress using a variety of metrics, including bugs and coverage.
Use EDA tools such as Cadence Xcelium for simulation, VManager for test plan development, Virtuoso for schematic viewing, Jasper Gold for formal verification and Verdi for waveform viewing and debugging.