Design Verification Engineer

Apple•Cupertino, CA

34d•$150,400 - $225,300•Onsite

About The Position

Imagine what you can do here. Apple is a place where extraordinary people gather to do their lives best work. Together we create products and experiences people once couldn't have imagined, and now, can't imagine living without. It's the diversity of those people and their ideas that inspires the innovation that runs through everything we do. Ensure bug-free first silicon for part of the SoC/IP. Develop detailed test and coverage plans based on the micro-architecture. Develop verification methodology suitable for the IP, ensuring a scalable and portable environment. Develop verification environment, including all the respective components such as stimulus, checkers, assertions, trackers, coverage. Learn to develop verification plans for all features under executing verification plans, including design bring-up, DV environment bring-up, regression enabling all feature and debugging of the test failures. Develop block, IP and SoC level test-benches track and report DV progress using a variety of metrics, including bugs and coverage. Writing scripts in Python or TCL. Developing stimulus and checkers to ensure analog and digital circuit interactions work seamlessly.

Requirements

Using Digital design and analog knowledge to create architecture and micro-architecture for the designs.
Using Verilog knowledge to create synthesizable digital designs and test-benches to verify the designs.
Using C and C++ to create reference models of the design under test to accurately predict design behavior.
Utilizing python for data analysis/processing, visualization, and machine learning implementation.
Executed chip design flow from specification to verification closure.
Experience with matlab programming to analyze probabilistic modelling and data analysis.
Using scripting languages like Perl or Python to create executable scripts.

Responsibilities

Ensure bug-free first silicon for part of the SoC/IP.
Develop detailed test and coverage plans based on the micro-architecture.
Develop verification methodology suitable for the IP, ensuring a scalable and portable environment.
Develop verification environment, including all the respective components such as stimulus, checkers, assertions, trackers, coverage.
Develop verification plans for all features under executing verification plans, including design bring-up, DV environment bring-up, regression enabling all feature and debugging of the test failures.
Develop block, IP and SoC level test-benches track and report DV progress using a variety of metrics, including bugs and coverage.
Writing scripts in Python or TCL.
Developing stimulus and checkers to ensure analog and digital circuit interactions work seamlessly.