Design Verification Engineer

Apple•San Diego, CA

18d•$142,300 - $214,300•Onsite

About The Position

Apple Inc. is seeking a Design Verification Engineer in San Diego, California. This role involves bringing up emulation platforms for large Wireless and Display SoCs with mixed-signal components. The engineer will develop monitors and checkers for the emulation platform, aiming for improved performance. Responsibilities include preparing and executing test plans, conducting reviews with cross-functional teams, and collaborating with Design, Architecture, Power, Silicon Validation, Performance, and SW Teams. The role requires developing code for design and verification using Verilog/System Verilog/UVM to aid emulation activities. This includes creating and bringing up emulation models, porting mixed-signal components to emulators (Palladium, Protium, Zebu, Veloce), writing System Verilog or Verilog monitors and checkers, and System Verilog Assertions. The engineer will utilize C-DPI and System Verilog-based transactors and monitors, understand specifications to create system-level test plans for emulation verification, and perform test plan reviews. Creating test benches and test cases using System Verilog, UVM, and Python scripting, and automating these using Python or Perl are key. The role also involves running test cases, debugging on emulation platforms, triaging failing tests, filing bugs, and working with design teams for resolution. Analyzing regressions using splunk databases, collecting coverage, and collaborating with designers to close verification activities are also part of the job. Additionally, the engineer will work with Silicon Validation teams to recreate and debug silicon issues, and with methodology teams to validate new tool versions used in emulation.

Requirements

Master’s degree or foreign equivalent in Electrical, Electrical and Computer Engineering, or related field.
Utilizing Verilog/System Verilog to create behavioral models for verification purpose
Understanding of computer architecture to learn into ASIC/SoC architectures
Utilizing Scripting tools including Perl, or Python, or Shell to write scripts
Understanding design of digital logic systems
Knowledge of ASIC Design and tools for simulation to verify and debug SoC
Using/applying Design Verification functional coverage for verification closure
Debugging test failures using logs and waveforms such as Verdi, Indago, or Simvision
Use of a standard simulation tool such as Cadence’s Xcelium, or Synopsys’s VCS to run simulations
Applying fundamentals of Digital Design while verifying the SoC design
Using UVM methodology to create constraint random benches

Nice To Haves

Responsibilities

Bring up emulation platform for large Wireless Socs along with their mixed signal components.
Develop monitors and checkers for Emulation platform and come up with the latest techniques to achieve better performance.
Prepare and execute the test plan and perform reviews with the cross-functional teams.
Collaborate cross functionally with Design, Architecture, Power, Silicon Validation, Performance and SW Teams.
Develop code for Design and verification that aids with emulation activities, using Verilog/System Verilog/UVM.
Create and bring up emulation models for Large Wireless Socs and Display Socs.
Port Mixed signal components into emulation models for emulators including Palladium, Protium, Zebu, and Veloce.
Write System Verilog or Verilog monitors and checkers.
Write System Verilog Assertions for emulation models.
Utilize C-DPI and System Verilog based transactors and monitors for emulation purposes.
Understand specifications and create system level Test Plans for emulation verification.
Perform Test Plan reviews with Design, Power, Architecture, System and Firmware teams.
Create test benches and test cases using System Verilog, UVM and Python script.
Automate Test Bench and test cases using Python, Perl.
Run test cases and debug on emulation platforms.
Debug and triage failing tests and file bugs, work with design teams to resolve.
Analyze regressions by extracting information from splunk databases.
Collect coverage and work with designers to close the verification activities.
Work with Silicon Validation teams to recreate and debug Silicon Issues.
Work with methodology teams to validate new versions of the tools used in emulation.