Design Verification Engineer

Apple • San Diego, CA

4d

About The Position

As a member of Apple’s design verification group, the Design Verification Engineer will help produce fully functional first silicon for IP designs and contribute to upcoming Apple products. The role covers pre-silicon verification, including establishing verification methodology, developing test plans and scalable, portable verification environments, writing tests, debugging, collecting coverage, and signing off for RTL freeze and tape-out. The engineer is responsible for verifying part of an SoC or IP and developing detailed test and coverage plans based on its microarchitecture.

The position involves creating verification-environment components such as stimulus, checkers, assertions, trackers, and coverage. The engineer will develop and execute plans for features under their care, bring up designs and DV environments, enable regressions, debug failures, close bugs, and track and report progress using metrics such as bugs and coverage. The role also includes developing block-, IP-, and SoC-level testbenches and using LLMs and related technologies to improve verification efficiency and quality.

Requirements

• Bachelor’s degree in a technical subject area, with a minimum of 10 years of proven experience or equivalent.
• Deep knowledge of object-oriented programming, SystemVerilog, and UVM.
• Deep knowledge of developing scalable and portable testbenches.
• Strong experience with verification methodologies and tools, including simulators, waveform viewers, build-and-run automation, coverage collection, and gate-level simulations.
• Working experience using LLMs for efficiency and quality.
• Experience with power-aware (UPF) or similar verification methodology.
• Excellent knowledge of at least one scripting language, such as Python, Perl, or TCL.

Nice To Haves

• Experience with serial protocols such as PCIe or USB, or parallel protocols such as DDR.
• Knowledge of formal verification methodology.
• Knowledge of emulation for verification technologies.

Responsibilities

• Study design specifications and create test plans.
• Establish verification methodology appropriate to the IP and develop scalable, portable environments.
• Develop SystemVerilog/UVM infrastructure and testbenches to stress the design.
• Develop verification-environment components, including stimulus, checkers, assertions, trackers, and coverage.
• Execute verification plans, including design and DV-environment bring-up and regression enablement.
• Develop tests, debug regression failures, and close bugs.
• Collect coverage and provide sign-off for RTL freeze and tape-out.
• Track and report verification progress using metrics such as bugs and coverage.
• Use LLMs and related technologies to improve verification efficiency and quality.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior