Design Verification Engineer

Apple • Cupertino, CA

1d • $174,149 - $225,300 • Hybrid

About The Position

Apple is a place where extraordinary people gather to do their lives best work. Together we create products and experiences people once couldn't have imagined, and now, can't imagine living without. It's the diversity of those people and their ideas that inspires the innovation that runs through everything we do. This role involves working with architecture and design teams to review design requirements, develop architectural specifications, and check specifications for correctness. The engineer will develop SystemVerilog based golden reference models to mimic the logical behaviors of RTL designs, according to the specification. They will also develop SystemVerilog assertions and checkers for testing the RTL design, and create assembly language or Perl and Python based directed tests and constrained random stimulus for design features. Running test simulations of RTL design using simulator and emulator tools, debugging failures, and working with the RTL design team on fixing bugs are key responsibilities. Additionally, the role includes developing coverage constructs, collecting coverage from RTL regressions, and reviewing code and functional coverage. Involvement in formal verification using the Jasper formal tool, developing manual or automated formal checks, running checks through the formal verification tool, and debugging failures are also part of the job. Developing Perl and Python scripts for automating different parts of the testing environment, summarizing failures from regressions, developing formal connectivity checks, and auto-filing tickets from regression reports are also expected.

Requirements

• Master's degree or foreign equivalent in Electrical and Computer Engineering, Electrical Engineering, Electronics Engineering, or a related field.
• Basic semiconductor physics.
• CMOS and/or VLSI Design
• Computer and Processor Architecture Design
• Design verification and functional coverage
• Developing RTL for digital logic blocks using SystemVerilog, including linting and synthesis readiness.
• Low-power techniques including clock gating, power gating, and multi-voltage designs
• Experience in computer architecture specification and performance analysis, including determining initial microarchitecture specification of a design.
• Object oriented programming, C, C++, System Verilog, Python, Perl, and algorithm
• Parallel Computer Architecture
• Test and scripting: Perl, Tcl, shell, Makefile, and Python

Responsibilities

• Work with architecture and design teams to review design requirements, develop architectural specifications and check specifications for correctness.
• Develop system Verilog based golden reference model to mimic the logical behaviors of RTL designs, according to the specification.
• Develop system Verilog assertions and checkers for testing the RTL design.
• Develop assembly language or Perl and Python based directed tests and constrained random stimulus for design features.
• Run test simulations of RTL design using simulator and emulator tools.
• Debug failures observed in RTL simulations and work with RTL design team on fixing the bugs.
• Develop coverage constructs; collect coverage from RTL regressions and review code, functional coverage.
• Involved in the formal verification of our design using jasper formal tool.
• Develop manual or automated formal checks to better verify the design.
• Run the checks through formal verification tool and debug any failures observed.
• Develop Perl and Python scripts for automating different part of the testing environment.
• Summarize failures from regressions, develop formal connectivity checks, auto file tickets from regression reports.

Benefits

• Comprehensive medical and dental coverage
• Retirement benefits
• A range of discounted products and free services
• Reimbursement for certain educational expenses — including tuition
• Discretionary bonuses or commission payments
• Relocation assistance
• Discretionary employee stock programs
• Discretionary restricted stock unit awards
• Purchase Apple stock at a discount if voluntarily participating in Apple’s Employee Stock Purchase Plan

What This Job Offers

• Job Type: Full-time
• Career Level: Senior